Z80185 Datasheet, PDF (82/95 Pages) Zilog, Inc. – SMART PERIPHERAL CONTROLLERS

Zilog
PRELIMINARY
Z80185/Z80195
SMART PERIPHERAL CONTROLLERS
Table 6. Data Bus Direction (Z185 Bus Master)
I/O and Memory Transactions
Z80185
Data Bus
(ROME=0)
Z80185
Data Bus
(ROME=1)
I/O Write
to On-Chip
Peripherals
Out
Out
I/O Read
from On-Chip
Peripherals
I/O Write
I/O Read
Read From Read From
to Off-Chip from Off-Chip Write to On-Chip Off-Chip
Z80185
Peripherals Peripherals Memory ROM
Memory Refresh Idle Mode
Z
Out
In
Out
Z
In
Z
Z
Out
Out
In
Out
Out
In
Z
Z
Interrupt Acknowledge Transaction
Z80185
Data Bus
(ROME=0)
Z80185
Data Bus
(ROME=1)
Intack for
On-Chip
Peripheral
Z
Out
Intack for
Off-Chip
Peripheral
In
In
Table 8. Data Bus Direction (Z185 Is Not Bus Master)
I/O and Memory Transactions
Z80185
Data Bus
(ROME=0)
Z80185
Data Bus
(ROME=1)
I/O Write
I/O Read
I/O Read
I/O Write
Read From Read From
Ext.
to On-Chip from On-Chip from Off-Chip to On-Chip Write to On-Chip Off-Chip
Bus Master
Peripherals Peripherals Peripherals Peripherals Memory ROM
Memory Refresh is Idle
In
Out
Z
Z
Z
Out
In
Z
Z
In
Out
Z
Z
Z
Out
In
Z
Z
Interrupt Acknowledge Transaction
Z80185
Data Bus
(ROME=0)
Z80185
Data Bus
(ROME=1)
Intack for
On-Chip
Peripheral
Out
Out
Intack for
Off-Chip
Peripheral
In
In
Notes:
"Out" means that the Z185 data bus direction is in output mode; "In" means
input mode, and "Z" means High impedance. ROME stands for ROM
Emulator mode and is the status of the D2 bit in the System Configuration
Register.
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DS971850301