Z80185 Datasheet, PDF (42/95 Pages) Zilog, Inc. – SMART PERIPHERAL CONTROLLERS

Zilog
PRELIMINARY
ACSI TIME CONSTANT REGISTERS
New Z8S180 Registers
Z80185/Z80195
SMART PERIPHERAL CONTROLLERS
7 6 54 3 21 0
7 6 54 3 21 0
Register: ASCI0 Time Constant Low
Address: 1Ah
Register: ASCI1 Time Constant Low
Address: 1Ch
7 6 54 3 21 0
Register: ASCI0 Time Constant High
Address: 1Bh
7 6 54 3 21 0
Register: ASCI1 Time Constant High
Address: 1Dh
CSI/O REGISTERS
CNTR
Bit EF EIE RE TE -
Upon Reset
R/W
0
0
0
0
1
R R/W R/W R/W
Addr 0AH
SS2 SS1 SS0
1 11
R/W R/W R/W
Speed Select
Transmit Enable
Receive Enable
End Interrupt Enable
End Flag
SS2, 1, 0
000
001
010
011
Baud Rate
Ø ÷ 20
Ø ÷ 40
Ø ÷ 80
Ø ÷ 100
SS2, 1, 0
100
101
110
111
Baud Rate
Ø ÷ 320
Ø ÷ 640
Ø ÷ 1280
External Clock
(Frequency < Ø ÷ 20)
Figure 34. CSI/O Control Register
TRDR
Read/Write
Addr 0BH
7 6 54 3 21 0
Read - Received Data
Write - Transmit Data
Figure 35. CSI/O Transmit/Receive Data Register
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DS971850301