Z80185 Datasheet, PDF (59/95 Pages) Zilog, Inc. – SMART PERIPHERAL CONTROLLERS

Zilog
EMSCC REGISTERS
PRELIMINARY
Z80185/Z80195
SMART PERIPHERAL CONTROLLES
Write Register 0 (non-multiplexed bus mode)
D7 D6 D5 D4 D3 D2 D1 D0
Write Register 2
D7 D6 D5 D4 D3 D2 D1 D0
0 0 0 Register 0
0 0 1 Register 1
0 1 0 Register 2
0 1 1 Register 3
1 0 0 Register 4
1 0 1 Register 5
1 1 0 Register 6
1 1 1 Register 7
0 0 0 Register 8
0 0 1 Register 9
0 1 0 Register 10
0 1 1 Register 11
1 0 0 Register 12
*
1 0 1 Register 13
1 1 0 Register 14
1 1 1 Register 15
0 0 0 Null Code
0 0 1 Point High
0 1 0 Reset Ext/Status Interrupts
0 1 1 Send Abort (SDLC)
1 0 0 Enable Int on Next Rx Character
1 0 1 Reset Tx Int Pending
1 1 0 Error Reset
1 1 1 Reset Highest IUS
0 0 Null Code
0 1 Reset Rx CRC Checker
1 0 Reset Tx CRC Generator
1 1 Reset Tx Underrun/EOM Latch
* ^{With Point High Command}
V0
V1
V2
V3
Interrupt
V4
Vector
V5
V6
V7
Write Register 3
D7 D6 D5 D4 D3 D2 D1 D0
0 0 Rx 5 Bits/Character
0 1 Rx 7 Bits/Character
1 0 Rx 6 Bits/Character
1 1 Rx 8 Bits/Character
Rx Enable
Sync Character Load Inhibit
Address Search Mode (SDLC)
Rx CRC Enable
Enter Hunt Mode
Auto Enables
Write Register 1
D7 D6 D5 D4 D3 D2 D1 D0
Ext Int Enable
Tx Int Enable
Parity is Special Condition
0 0 Rx Int Disable
0 1 Rx Int On First Character or Special Condition
1 0 Int On All Rx Characters or Special Condition
1 1 Rx Int On Special Condition Only
Reserved,
Program as 00.
WAIT Request Enable
Write Register 4
D7 D6 D5 D4 D3 D2 D1 D0
Parity Enable
Parity EVEN//ODD
0 0 Sync Modes Enable
0 1 1 Stop Bit/Character
1 0 1 1/2 Stop Bits/Character
1 1 2 Stop Bits/Character
0 0 8-Bit Sync Character
0 1 16-Bit Sync Character
1 0 SDLC Mode (01111110 Flag)
1 1 External Sync Mode
0 0 X1 Clock Mode
0 1 X16 Clock Mode
1 0 X32 Clock Mode
1 1 X64 Clock Mode
Figure 68. Write Register Bit Functions
DS971850301
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