Z80185 Datasheet, PDF (33/95 Pages) Zilog, Inc. – SMART PERIPHERAL CONTROLLERS

Zilog
PRELIMINARY
Z80185/Z80195
SMART PERIPHERAL CONTROLLES
Z8S180 POWER-DOWN MODES
The following is a detailed description of the enhance-
ments to the Z8S180 from the standard Z80180 in the areas
of STANDBY, IDLE, and STANDBY-QUICK RECOVERY
modes.
Add-On Features
There are five different power-down modes. SLEEP and
SYSTEM STOP are inherited from the Z80180. In SLEEP
Notes:
† _{IDLE and STANDBY modes are only offered in the Z8S180. Note that the}
minimum recovery time can be achieved if INTERRUPT is used as the
Recovery Source.
mode, the CPU is in a stopped state while the on-chip
I/Os are still operating. In I/O STOP mode, the on-chip I/Os
are in a stopped state while leaving the CPU running. In
SYSTEM STOP mode, both the CPU and the on-chip I/Os
are in the stopped state to reduce current consumption.
The Z8S180 has added two additional power-down modes,
STANDBY and IDLE, to reduce current consumption even
further. The differences in these power-down modes are
summarized in Table 2.
STANDBY Mode
The Z8S180 is designed to save power. Two low-power
programmable power-down modes have been added:
STANDBY mode and IDLE mode. The STANDBY/IDLE
mode is selected by multiplexing D6 and D3 of the CPU
Control Register (CCR, I/O Address = 1FH).
To enter STANDBY mode:
oscillator stabilization. When the part receives an external
IRQ or BUSREQ during STANDBY mode, the oscillator is
restarted and the timer counts down 2¹⁷ counts before
acknowledgment is sent to the interrupt source.
The recovery source needs to remain asserted for the
duration of the 2¹⁷ count, otherwise standby will be re-
1. Set D6 and D3 to 1 and 0, respectively.
2. Set the I/O STOP bit (D5 of ICR,
I/O Address = 3FH) to 1.
3. Execute the SLEEP instruction.
When the device is in STANDBY mode, it behaves similar
to the SYSTEM STOP mode as it exists on the Z80180,
except that the STANDBY mode stops the external oscilla-
tor, internal clocks and reduces power consumption to
50 µA (typical).
Since the clock oscillator has been stopped, a restart of
the oscillator requires a period of time for stabilization. An
18-bit counter has been added in the Z8S180 to allow for
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