Z80185 Datasheet, PDF (76/95 Pages) Zilog, Inc. – SMART PERIPHERAL CONTROLLERS

Zilog
PRELIMINARY
Z80185/Z80195
SMART PERIPHERAL CONTROLLERS
Peripheral ECP Forward Modes
1. After a negotiation for ECP mode, “peripheral” software
should remain in Compatibility/Negotiation mode with
P1284Active (nSelectIn) High, so that it has complete
control of the interface, though when it detects the host
drive HostAck (nAutoFd) Low for the second time, it
should then set nAckReverse (PError) High. If software
has data to send, it should drive nPeriphRequest (nFault)
Low at the same time, and optionally program a DMA
channel to provide the data. Whether or not it has data
to send, software should then set one of the two ECP
Forward modes.
2. In these modes, the controller configures PIA27-20 as
inputs regardless of the contents of register E2. On
entry to one of these modes, the controller clears the
Idle bit, if it had been set.
3. For each byte, the controller waits for the host to drive
HostClk (nStrobe) to Low. When HostClk (nStrobe) is
Low and software, or the DMA channel, has taken any
previous byte and thus cleared DREQ, operation di-
verges into four cases depending on the state of
HostAck (nAutoFd), the mode, the MSbit of the data,
and the state of an internal 7-bit Run-Length Encoding
(RLE) counter.
5. Thereafter, the controller waits for the host to drive
HostClk (nStrobe) back to High, at which time it drives
PeriphAck (Busy) back to Low, and returns to the event
sequence at the start of paragraph #3.
6. If HostAck (nAutoFd) is Low, and PIA27 is High, the byte
is a “channel address." In this case, or when PIA27 is
Low and the mode is “software RLE handling," the
controller captures the data from PIA27-20 into the
Input/Output Register, leaves DREQ cleared to keep a
DMA channel from storing the byte, and sets the Idle bit,
which it does not otherwise set while in this mode.
Software should respond to this condition by reading
the byte from the PIA 2 data register E3. Software can
then do whatever else is needed to handle the situation,
and then set Busy High. Thereafter the controller clears
Idle, waits (if necessary) for the host to drive HostClk
(nStrobe) back to High, and then drives PeriphAck
(Busy) back to Low and returns to the event sequence
at the start of paragraph #3.
While this mode is set, if data to send becomes available,
software should drive nPeriphRequest (nFault) Low to alert
the host of this fact. Also software should monitor the
controller for either of two conditions:
If HostAck (nAutoFd) is High, indicating that this byte is
neither an RLE value, nor a Channel Address, the control-
ler captures the data from PIA27-20 into the Input/Output
Register, sets DREQ to request software, or the DMA
channel, to take this byte, and drives PeriphAck (Busy)
High. If the RLE counter is zero, the controller waits (if
necessary) for the host to drive HostClk (nStrobe) back to
High, after which it drives PeriphAck (Busy) back to Low
and returns to the event sequence at the start of paragraph
#3. If the RLE counter is non-zero, the controller waits for
software, or a DMA channel, to read the byte from the
Input/Output Register, negates DREQ only momentarily,
and decrements the RLE counter. It does this until the RLE
counter is zero, at which point it proceeds as described
above. Thus an RLE value of “n” results in the next byte
being provided to software, or a DMA channel “n+1” times.
4. If HostAck (nAutoFd) is Low and the MS bit of the byte
is zero (PIA27 is Low), the byte is an RLE repeat count.
If the mode is “hardware RLE expansion," the controller
transfers (the seven LS bits of) it to the RLE counter,
leaves DREQ cleared, and drives PeriphAck (Busy)
High.
a. If the host drives nReverseRequest (nInit) Low in re-
sponse to nPeriphRequest (nFault) Low, software should
drive nAckReverse (PError) Low, optionally program a
DMA channel to provide the data, and set Peripheral
ECP Reverse mode.
b. If P1284Active (nSelectIn) goes Low, the controller sets
the IllOp bit in PARC, if this occurs between the time the
host drives HostClk (nStrobe) Low, and when the con-
troller subsequently drives PeriphAck (Busy) back to
Low, in which case software should immediately enter
Peripheral Compatibility/Negotiation mode. If P1284Ac-
tive goes Low, but IllOp stays zero, indicating a “legal”
termination, software should enter Peripheral Inactive
mode and sequence the nAckReverse (PError),
PeriphAck (Busy), PeriphClk (nAck), nPeriphRequest
(nFault), and Xflag (Select) lines to leave ECP mode.
Status interrupts in Peripheral ECP Forward mode include
rising and falling edges on P1284Active (nSelectIn) and
nReverseRequest (nInit).
76
DS971850301