Z80185 Datasheet, PDF (81/95 Pages) Zilog, Inc. – SMART PERIPHERAL CONTROLLERS

Zilog
PRELIMINARY
Z80185/Z80195
SMART PERIPHERAL CONTROLLES
Z80185 PIA AND MISCELLANEOUS REGISTERS (Continued)
System Configuration Register (Continued)
Bit 7. Decode High I/O. If this bit is 0, as it is after a Reset,
A15-8 are not decoded for the registers for which A7-6 are
11, that is, the registers for the EMSCC, CTCs, I/O Ports,
Bidirectional Centronics Controller. If this bit is 1, A15-8
must all be zero to access these registers, as for the other
registers in the Z80185. When set to 0, this bit is compatible
with the Z80181 and Z80182, and allows shorter, and more
basic I/O instructions to be used to access these registers.
Alternately, when set to 1, this bit allows more extensive off-
chip I/O.
Bit 6. Daisy-Chain Configuration Bit 2. This bit is described
with bits 1-0 below.
Bit 5. Disable /ROMCS. When this bit is 1, /ROMCS is
forced to High, regardless of the status of the address
decode logic. This bit Resets to 0 so that /ROMCS is
enabled.
Bit 4. When this bit is 0, the /RTS0/TXS, /CTS0/RXS, and
CKA0/CKS pins have the /RTS0, /CTS0 and CKA0 func-
tions, respectively. When this bit is 1, the pins have the
TXS, RXS, and CKS functions, and the CSIO facility can be
used. When this bit is 1, if ASCI0 is used, the “CTS auto-
enable” function must not be enabled. The multiplexing of
CKA0 is important only with respect to output — the same
external clock could be used for both ASCI0 and the CSIO.
Bit 3. When this bit is 0, the PCLK clock of the EMSCC is
the same as the processor’s PHI clock. When this bit is 1,
this clock is PHI/2. Set this bit if the PHI clock is too fast for
the EMSCC.
Bit 2. ROM Emulator Mode Enable. When this bit is 1, read
data from on-chip sources is driven onto the D7-D0 pins,
as shown in Table 6. This bit resets to 0.
Bits 1-0. These bits, plus bit 6, determine the routing of the
on-chip interrupt daisy-chain, and thus the relative inter-
rupt priority of the on-chip interrupt sources on the daisy-
chain as shown in Table 5.
b6
b1
b0
0
0
0
0
0
1
0
1
X
1
0
0
1
0
1
1
1
X
Table 5. Interrupt Daisy-Chain Routing
Daisy Chain Configuration
IEI pin -> EMSCC -> CTC -> Bidirectional Centronics Controller -> IEO pin
IEI pin -> EMSCC -> Bidirectional Centronics Controller -> CTC -> IEO pin
IEI pin -> Bidirectional Centronics Controller -> EMSCC -> CTC -> IEO pin
IEI pin -> CTC -> EMSCC -> Bidirectional Centronics Controller -> IEO pin
IEI pin -> CTC -> Bidirectional Centronics Controller -> EMSCC -> IEO pin
IEI pin -> Bidirectional Centronics Controller -> CTC -> EMSCC -> IEO pin
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