Z80185 Datasheet, PDF (78/95 Pages) Zilog, Inc. – SMART PERIPHERAL CONTROLLERS

Zilog
PRELIMINARY
Z80185/Z80195
SMART PERIPHERAL CONTROLLERS
Peripheral ECP Reverse Mode
1. In this mode, as long as nReverseRequest (nInit) is Low,
and P1284Active (nSelectIn) is High, the controller
drives the contents of the Input/Output Register onto
PIA27-20, regardless of the contents of the E2 register.
On entry to this mode, the controller sets Idle, and sets
DREQ to request data from software, or a DMA channel.
2. If software, or a DMA channel, writes data to the Output
Holding Register while the Input/Output Register is
empty, the controller immediately transfers the byte to
the IOR, clears Idle, and negates DREQ only momen-
tarily, to request another byte.
3. In this mode, an alternate address for the Output
Holding Register allows software to send a “channel
address” or an RLE count value. Such bytes are not
typically written by a DMA channel. Writing to this
alternate address loads the OHR and clears DREQ, the
same as writing to the primary address, but clears a
ninth bit set when software, or a DMA channel, writes to
the primary address. A similar ninth bit is associated
with the IOR, and drives the PeriphAck (Busy) line in this
mode.
4. As each nine bits arrive in the IOR, and thus out onto
PIA27-20 and PeriphAck (Busy), the controller waits
one PHI clock, and then drives PeriphClk (nAck) Low.
It then waits for the host to drive HostAck (nAutoFd)
High, after which it drives PeriphClk (nAck) back to
High. The controller then waits for the host to drive
HostAck (nAutoFd) back to Low. When this has hap-
pened, if software, or the DMA channel, has written a
new byte to the Output Holding Register, and thus
cleared DREQ, the controller transfers the byte to the
IOR, sets DREQ again, and returns to the start of the
event sequence in this paragraph. Otherwise, it returns
to the event sequence at the start of paragraph #2. If
software, or the DMA channel, doesn’t provide new
data within the time indicated by the PART register, the
controller sets the Idle bit.
5. While this mode is in effect, software should monitor
whether the host drives nReverseRequest (nInit) High.
If it detects this, it should set the mode back to Periph-
eral ECP Forward, wait 500 ns and then drive
nAckReverse (PError) back to High, before proceeding
as described for Peripheral ECP Forward mode above.
6. Status interrupts in Peripheral ECP Reverse mode in-
clude rising and falling edges on P1284Active
(nSelectIn) and nReverseRequest (nInit). Since there
are no “legal terminations” during the time this mode is
set, the controller sets IllOp for any falling edge on
P1284Active (nSelectIn) in this mode.
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