Z80185 Datasheet, PDF (48/95 Pages) Zilog, Inc. – SMART PERIPHERAL CONTROLLERS

Zilog
DMA REGISTERS (Continued)
PRELIMINARY
Z80185/Z80195
SMART PERIPHERAL CONTROLLERS
Bit
Upon Reset
R/W
DMODE
-
-
1
1
Addr 31H
DM1 DM0 SM1 SM0 MMOD -
0
0
0
0
0
1
R/W R/W R/W R/W R/W
Memory MODE Select
Ch 0 Source Mode 1, 0
Ch 0 Destination Mode 1, 0
DM1, 0
00
01
10
11
Destination
M
M
M
I/O
Address
DAR0+1
DAR0-1
DAR0 Fixed
DAR0 Fixed
MMOD
0
1
Mode
Cycle Steal Mode
Burst Mode
SM1, 0
00
01
10
11
Source
M
M
M
I/O
Address
SAR0+1
SAR0-1
SAR0 Fixed
SAR0 Fixed
Figure 55. DMA Mode Registers
48
DS971850301