Z80185 Datasheet, PDF (28/95 Pages) Zilog, Inc. – SMART PERIPHERAL CONTROLLERS

Zilog
PRELIMINARY
Z80185/Z80195
SMART PERIPHERAL CONTROLLERS
Timing &
Ø
Clock
Generator
TOUT/
/DREQ
/RTS0/TxS
/CTS0/RxS
CKA0/CKS
16-Bit
Programmable
Reload Timers
(2)
Clocked
Serial I/O
Port
MMU
Bus State Control
CPU
Interrupt
DMACs
(2)
TOUT//DREQ
Asynchronous
SCI
(Channel 0)
Asynchronous
SCI
(Channel 1)
TxA0
CKA0/CKS
RxA0
/RTS0
/CTS0
/DCD0
TxA1
DCD0/CKA1
RxA1
A19-A0
D7-D0
Figure 21. Z8S180 MPU Block Diagram
28
DS971850301