Z80185 Datasheet, PDF (19/95 Pages) Zilog, Inc. – SMART PERIPHERAL CONTROLLERS

Zilog
PRELIMINARY
AC CHARACTERISTICS (Continued)
EMSCC General Timing
No.
Symbol
Parameter
2
TdPC(W)
/PCLK to Wait Inactive
3
TsRxC(PC)
/RxC to /PCLK Setup Time
4
TsRxD(RxCr)
RxD to /RxC Setup Time
5
ThRxD(RxCr)
RxD to /RxC Hold Time
6
TsRxD(RxCf)
RxD to /RxC Setup Time
7
ThRxD(RxCf)
RxD to /RxC Hold Time
10
TsTxC(PC)
/TxC to /PCLK Setup Time
11
TdTxCf(TXD)
/TxC to TxD Delay
12
TdTxCr(TXD)
/TxC to TxD Delay
13
TdTxD(TRX)
TxD to TRxC Delay
14
TwRTxh
RTxC High Width
15
TwRTxI
TRxC Low Width
16a
TcRTx
16b
TxRx(DPLL)
17
TcRTxx
18
TwTRxh
RTxC Cycle Time
DPLL Cycle Time Min
Crystal OSC. Period
TRxC High Width
19
TwTRxl
20
TcTRx
21
TwExT
TRxC Low Width
TRxC Cycle Time
DCD or CTS Pulse Width
Notes:
[1] RxC is /RTxC or /TRxC, whichever is supplying the receive clock.
[2] TxC is /TRxC or /RTxC, whichever is supplying the transmit clock.
[3] Both /RTxC and /SYNC have 30 pF capacitors to Ground connected to them.
[4] Synchronization of RxC to PCLK is eliminated in divide-by-four operation.
[5] Parameter applies only to FM encoding/decoding.
[6] Parameter applies only for transmitter and receiver; DPLL and baud
rate generator timing requirements are identical to case PCLK requirements.
[7] The maximum receive or transmit data rate is 1/4 PCLK.
[8] Applies to DPLL clock source only. Maximum data rate of 1/4 PCLK
still applies. DPLL clock should have a 50% duty cycle.
These AC parameter values are preliminary and subject to change without notice.
Z80185/Z80195
SMART PERIPHERAL CONTROLLES
20 MHz
Min
Max
170
NA
0
45
0
45
NA
70
70
80
70
70
200
50
61
1000
70
70
200
60
Notes
[1,4]
[1]
[1]
[1,5]
[1,5]
[2,4]
[2]
[2,5]
70
[6]
[6]
[6,7]
[7,8]
[3]
[6]
[6]
[6,7]
DS971850301
19