Z80185 Datasheet, PDF (50/95 Pages) Zilog, Inc. – SMART PERIPHERAL CONTROLLERS

Zilog
PRELIMINARY
SYSTEM CONTROL REGISTERS
Z80185/Z80195
SMART PERIPHERAL CONTROLLERS
IL
Addr 33H
Bit
IL7 IL6 IL5 -
-
-
-
-
Upon Reset
00000000
R/W
R/W R/W R/W
Interrupt Vector Low
Figure 57. Interrupt Vector Low Register
ITC
Bit
TRAP UFO -
-
Upon Reset
0011
R/W R/W R
Addr 34H
- ITE2 ITE1 ITE0
1001
R/W R/W R/W
Figure 58. INT/TRAP Control Register
/INT Enable 2, 1, 0
Undefined Fetch Object
TRAP
RCR
Addr 36H
Bit
REFE REFW ^-
-
-
- _{CYC1 CYC0}
Upon Reset
1
1
1
1
1
1
0
0
R/W
R/W R/W
R/W R/W
Cycle Select
Refresh Wait State
Refresh Enable
CYC1, 0 Interval of Refresh Cycle
00
10 states
01
20 states
10
40 states
11
80 states
Figure 59. Refresh Control Register
50
DS971850301