Z80185 Datasheet, PDF (12/95 Pages) Zilog, Inc. – SMART PERIPHERAL CONTROLLERS

Zilog
PRELIMINARY
AC CHARACTERISTICS
V
DD
=
5V
±
10%,
V
SS
=
0V,
CL
=
50
pF
for
outputs
over
specified temperature range, unless otherwise noted.
Z80185/Z80195
SMART PERIPHERAL CONTROLLERS
No. Symbol Parameter
Z80185 / Z80195
(20 MHz)
Min Max
1 tcy
2 tCHW
3 tCLW
4 tcf
5 tcr
6 tAD
Clock Cycle Time
Clock “H” Pulse Width
Clock “L” Pulse Width
Clock Fall Time
Clock Rise Time
PHI Rising to Address Valid
50 (DC)
15
15
10
10
30
7 tAS
Address Valid to (MREQ Falling or IORQ Falling) 5
8 tMED1 PHI Falling to MREQ Falling Delay
25
9a tRDD1 PHI Falling to RD Falling Delay (IOC=1)
25
9b tRDD1 PHI Rising to RD Falling Delay (IOC=0)
25
10 tM1D1 PHI Rising to M1 Falling Delay
35
11 tAH
Address Hold Time from (MREQ, IOREQ, RD, WR) 5
12 tMED2 PHI Falling to MREQ Rising Delay
25
13 tRDD2 PHI Falling to RD Rising Delay
25
14 tM1D2
15 tDRS
16 tDRH
17 tSTD1
18 tSTD2
19 tWS
20 tWH
PHI Rising to M1 Rising Delay
Data Read Setup Time
Data Read Hold Time
PHI Falling to ST Falling Delay
PHI Falling to ST Rising Delay
WAIT Setup Time to PHI Falling
WAIT Hold Time from PHI Falling
40
10
0
30
30
15
10
21 tWDZ
22 tWRD1
23 tWDD
24 tWDS
25 tWRD2
26 tWRP
26a tWRP
27 WDH
PHI Rising to Data Float Display
PHI Rising to WR Falling Delay
PHI Rising to Write Data Delay Time
Write Data Setup Time to WR Falling
PHI Falling to WR Rising Delay
Write Pulse Width (Memory Write Cycle)
Write Pulse Width (I/O Write Cycle)
Write Data Hold Time From (WR Rising)
Notes:
Specifications 1 through 5 refer to an external clock input on EXTAL, and
provisionally to PHI clock output. When a quartz crystal is used with the
on-chip oscillator, a lower maximum frequency than that implied by spec.
#1 may apply.
35
25
25
10
25
75
130
10
Z80185 / Z80195
(33 MHz)
Min Max Units
33 (DC)
ns
10
ns
10
ns
5
ns
5
ns
15
ns
5
ns
15
ns
15
ns
15
ns
15
ns
5
ns
15
ns
15
ns
15
ns
5
ns
0
ns
15
ns
15
ns
10
ns
5
ns
20
ns
15
ns
15
ns
10
ns
15
ns
45
ns
70
ns
5
ns
12
DS971850301