Z80185 Datasheet, PDF (53/95 Pages) Zilog, Inc. – SMART PERIPHERAL CONTROLLERS

Zilog
CPU CONTROL REGISTER
PRELIMINARY
Z80185/Z80195
SMART PERIPHERAL CONTROLLES
The CPU Control Register allows the programmer to select
options that directly affect the CPU performance as well as
controlling the STANDBY operating mode of the chip. The
CPU Control Register (CCR) allows the programmer to
change the divide-by-two internal clock to divide-by-one.
In addition, applications where EMI noise is a problem, the
Z8S180 can reduce the output drivers on selected groups
of pins to 33 percent of normal pad driver capability which
minimizes the EMI noise generated by the part (Figure 65).
CPU Control Register (CCR) Addr 1FH
D7 D6 D5 D4 D3 D2 D1 D0
00000000
Clock Divide
0 = XTAL/2
1 = XTAL/1
Standby/Idle Enable
00 = No Standby
01 = Idle After Sleep
10 = Standby After Sleep
11 = Standby After Sleep
64 Cycle Exit
(Quick Recovery)
BREXT
0 = Ignore BUSREQ
In Standby/Idle
1 = Standby/Idle Exit
on BUSREQ
New Z8S180 Register
LNAD/DATA
0 = Standard Drive
1 = 33% Drive On
A19-A0, D7-D0
LNCPUCTL
0 = Standard Drive
1 = 33% Drive On CPU
Control Signals
LNIO
0 = Standard Drive
1 = 33% Drive on Certain
External I/O
LNPHI
0 = Standard Drive
1 = 33% Drive On
EXT.PHI Clock
Figure 65. CPU Control Register
DS971850301
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