Z80185 Datasheet, PDF (55/95 Pages) Zilog, Inc. – SMART PERIPHERAL CONTROLLERS

Zilog
PRELIMINARY
Z80185/Z80195
SMART PERIPHERAL CONTROLLES
ON-CHIP ENHANCED SERIAL COMMUNICATIONS CONTROLLER (EMSCC)
The Z80185 contains a single-channel EMSCC which
features a 4-byte transmit FIFO and an 8-byte receive
FIFO, this enhancement reduces the overhead required to
provide data to, and get data from, the transmitter and
receiver. The EMSCC also improves packet handling in
SDLC mode to:
s automatically transmit a flag before the data;
s reset the Tx Underrun/EOM latch;
s force the TxD pin High at the appropriate time when
using NRZI encoding;
s deassert the /RTS pin after the closing flag;
and
s better handle ABORTed frames when using the 10x19
status FIFO.
The combination of these features, along with the data
FIFOs, significantly simplifies SDLC driver software.
s Write registers: WR3, WR4, WR5, and WR10 are now
readable
s Read Register 0 Latched During Access
s Many Improvements to Support SDLC/HDLC Transfers:
– Deactivation of /RTS Pin after Closing Flag
– Automatic Transmission of the Opening Flag
– Automatic Reset of Tx Underrun/EOM Latch
– Complete CRC Reception
– TxD pin Automatically Forced High with NRZI
Encoding when Using Mark Idle.
– Receive FIFO Automatically Unlocked for
Special Receive Interrupts when Using the
SDLC Status FIFO.
– Back-to-Back Frame Transmission Simplified
s Software Interrupt Acknowledge mode
The CPU hardware interface has been simplified by reliev-
ing the databus setup time requirement and supporting
the software generation of the interrupt acknowledge sig-
nal (/INTACK). These changes allow an interface with less
external logic to many microprocessor families while main-
taining compatibility with existing designs. I/O handling of
the EMSCC is improved over the SCC, with faster response
of the /DTR//REQ pin. The many enhancements added to
the EMSCC permits a system design that increases overall
system performance with better data handling and less
interface logic.
Significant features of the EMSCC include:
s Hardware and software compatible with Zilog's SCC/
ESCC
s DPLL Counter Output Available as Jitter-Free Clock
Source
s A Full-Duplex Channel with a Baud Rate Generator
and Digital Phase-Locked Loop
s Multi-Protocol Operation Under Program Control
s Asynchronous or Synchronous mode
In addition, the following features have been added to the
EMSCC channel in the Z80185:
s Programmable LocalTalk feature
s Non-Multiplexed /DTR Pin
s 4-Byte Transmit FIFO
s Internal Connection of DMA Request and /WAIT Signals
s 8-Byte Receive FIFO
s Programmable FIFO Interrupt Levels Provide Flexible
Interrupt Response
s EMSCC Programmable Clock
– Programmed to be Equal to System Clock
Divided by One or Two
– Programmed by System Configuration Register
s Improved SDLC Frame Status FIFO
s New Programmable Features Added with Write
Register 7'
Note: The EMSCC programmable clock must be pro-
grammed to divide-by-two mode when operating above
the following condition: PHI > 20 MHz at 5.0V
DS971850301
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