Z80185 Datasheet, PDF(73/95 Page) Zilog, Inc. – SMART PERIPHERAL CONTROLLERS

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Z80185 Datasheet, PDF (73/95 Pages) Zilog, Inc. – SMART PERIPHERAL CONTROLLERS

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Zilog

PRELIMINARY

Z80185/Z80195

SMART PERIPHERAL CONTROLLES

Z80185 BIDIRECTIONAL CENTRONICS P1284 CONTROLLER (Continued)

Peripheral Nibble Mode

1. Software shouldnât set this mode until there is reverse

data available to send. In other words, it should imple-

ment the P1284 âreverse idle modeâ via software in

Peripheral Compatibility/Negotiation mode. After soft-

ware has driven nDataAvail (nFault), AckDataReq

(PError), and Xflag (Select) all Low to signify that data

is available, then driven PtrClk (nAck) High after 500 ns,

and if requested programmed a DMA channel to pro-

vide data to send, when it sees HostBusy (nAutoFd)

Low to request data, software should set this mode.

Setting this mode sets DREQ and Idle, but these settings

do not request an interrupt. The PIA27-20 pins remain

configured for data input but are not used. Instead, four of

the five control outputs are driven with the LS and MS four

bits of the Input/Output Register, as shown in Table 2, while

PtrClk (nAck) serves as a handshake/clock output. On

entering this mode the hardware begins routing bits 3-0 of

the IOR to these lines.

2. If software, or a DMA channel, writes a byte to the

Output Holding Register when Idle is set, the controller

immediately transfers the byte to the IOR and clears

Idle, and negates DREQ only momentarily to request

another byte from software or the DMA channel.

3. After data has been valid on the four control outputs for

500 ns (as controlled by the PART register), the control-

ler drives the PtrClk (nAck) line Low. Then it waits for the

host to drive the HostBusy (nAutoFd) line back to High,

after which it drives PtrClk (nAck) back to High, switches

the four control lines to bits 7-4 of the IOR, and begins

waiting for the host to drive HostBusy (nAutoFd) back to

Low. When bits 7-4 have been valid for 500 ns and the

host has driven HostBusy (nAutoFd) Low, the controller

drives PtrClk (nAck) Low again and begins waiting for

the host to drive HostBusy (nAutoFd) High. When

HostBusy (nAutoFd) has been driven High, the control-

ler returns the four control outputs to the state set by

software in PARC. At this point, if software or a DMA

channel has not yet written another byte to the Output

Holding Register (thus clearing DREQ), the controller

sets Idle and waits for software to do so. If/when

software or a DMA channel has written a new byte to the

OHR, the controller transfers the byte to the IOR, sets

DREQ, and clears Idle if it had been set. Then, when the

control outputs have been valid for 500 ns, the control-

ler drives PtrClk (nAck) to High. It then waits for the host

to drive HostBusy (nAutoFd) back to Low, at which time

it switches the four control lines back to bits 3-0 of the

IOR and returns to the event sequence at the start of this

paragraph.

If there is no more data to send, when the controller sets

Idle, software should modify PARC to make nDataAvail

(nFault) and AckDataReq (PError) High, and then change

the mode to Peripheral Compatible/Negotiation. Then (af-

ter 500 ns) software should set PtrClk (nAck) back to High

in PARC and enter Reverse Idle state.

Status interrupts in Peripheral Nibble mode include rising

and falling edges on P1284Active (nSelectIn) and nInit.

The controller sets the IllOp (Illegal Operation) bit if

P1284Active (nSelectIn) goes Low in this mode, before it

drives nAck High for the status states on the four control

lines, or after the host drives HostBusy Low thereafter, in

which case software should immediately enter Peripheral

Compatibility/Negotiation mode. If P1284Active goes Low,

but IllOp stays 0, indicating that the Host negated

P1284Active in a legitimate manner, software should enter

Peripheral Inactive mode for the duration of the âreturn to

Compatibility modeâ, and then enter Peripheral Compat-

ibility/Negotiation mode.

Host Byte Mode

1. When in Host Negotiation mode the software has pre-

sented the value hex 01 or 05 on PIA27-20, it has been

acknowledged by the peripheral, and the peripheral

has driven nDataAvail (nFault) and AckDataReq (PError)

to Low to indicate data availability and then driven

PtrClk (nAck) back to High, software should set this

mode. This sets PIA27-20 as inputs regardless of the

contents of register E2, and clears the Idle flag. The

controller then waits 500 ns (as controlled by the PART

2. For each byte, the controller drives HostBusy (nAutoFd)

Low to indicate readiness for a byte from the peripheral.

Then it waits for PtrClk (nAck) to go Low, at which time

it captures the state of PIA27-20 into the Input/Output

DMA channel to take the byte, and drives HostBusy

(nAutoFd) High and HostClk (nStrobe) Low. When

software, or the DMA channel, has taken the byte (thus

clearing DREQ) and the peripheral has driven PtrClk

(nAck) back High, and at least 500 ns after driving

HostClk (nStrobe) Low, the controller drives HostClk

(nStrobe) back to High, and samples nDataAvail (nFault).

If it is still Low, the controller returns to the event

sequence at the start of this paragraph, otherwise it sets

the Idle flag.

DS971850301

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