Z80185 Datasheet, PDF (23/95 Pages) Zilog, Inc. – SMART PERIPHERAL CONTROLLERS

Zilog
PRELIMINARY
Z80185/Z80195
SMART PERIPHERAL CONTROLLES
PIN DESCRIPTIONS
Z80185 CPU Signals
A0-A19. Address Bus (input/output, active High, tri-state).
A0-A19 is a 20-bit address bus that provides the address
for memory data bus cycles up to 1 Mbyte, and I/O data
bus cycles up to 64 Kbytes. The address bus enters a High
impedance state during reset and external bus acknowl-
edge cycles. This bus is an input when /BUSACK is Low.
No address lines are multiplexed with any other signals.
D0-D7. Data Bus (bidirectional, active High, tri-state). D0-
D7 constitute an 8-bit bidirectional data bus, used to
transfer information to and from I/O and memory devices.
The data bus enters the High impedance state during reset
and external bus acknowledge cycles, as well as during
SLEEP and HALT states.
/RD. Read (input/output, active Low, tri-state). /RD indi-
cates that the CPU is ready to read data from memory or
an I/O device. The addressed I/O or memory device
should use this signal to gate data onto the CPU data bus.
This pin is tri-stated during bus acknowledge cycles.
/WR. Write (input/output, active Low, tri-state). /WR indi-
cates that the CPU data bus holds valid data to be stored
at the addressed I/O or memory location. This pin is tri-
stated during bus acknowledge cycles.
/IORQ. I/O Request (input/output, active Low, tri-state).
/IORQ indicates that the address bus contains a valid I/O
address for an I/O read or I/O write operation. /IORQ is also
generated, along with /M1, during the acknowledgment of
the /INT0 input signal to indicate that an interrupt response
vector can be placed onto the data bus. This pin is tri-
stated during bus acknowledge cycles.
/M1. Machine Cycle 1 (input/output, active Low). Together
with /MREQ, /M1 indicates that the current cycle is the
opcode fetch cycle of an instruction execution. Together
with /IORQ, /M1 indicates that the current cycle is for an
interrupt acknowledge. It is also used with the /HALT and
ST signal to indicate the status of the CPU machine cycle.
The processor can be configured so that this signal is
compatible with the /M1 signal of the Z80, or with the /LIR
signal of the Z64180. This pin is tri-stated during bus
acknowledge cycles.
/MREQ. Memory Request (input/output, active Low, tri-
state). /MREQ indicates that the address bus holds a valid
address for a memory read or memory write operation. It is
included in the /RAMCS and /ROMCS signals, and be-
cause of this may not be needed in some applications. This
pin is tri-stated during bus acknowledge cycles.
/WAIT. (input/open-drain output, active Low.) /WAIT indi-
cates to the MPU that the addressed memory or I/O
devices are not ready for a data transfer. This input is used
to induce additional clock cycles into the current machine
cycle. External devices should also drive this pin in an
open-drain fashion. This results in a “wired OR” of the Wait
indications produced by external devices and those pro-
duced by the two separate Wait State generators in the
Z80185. If the wire-ORed input is sampled Low, then
additional wait states are inserted until the /WAIT input is
sampled High, at which time the cycle is completed.
/HALT. Halt/Sleep Status (output, active Low). This output
is asserted after the CPU has executed either the HALT or
SLP instruction, and is waiting for either non-maskable or
maskable interrupt before operation can resume. It is also
used with the /M1 and /ST signals to indicate the status of
the CPU machine cycle. On exit of Halt/Sleep, the first
instruction fetch is delayed 16 clock cycles after the /HALT
pin goes High.
/BUSACK. Bus Acknowledge (output, active Low).
/BUSACK indicates to the requesting device that the MPU
address and data bus, as well as some control signals,
have entered their High impedance state.
/BUSREQ. Bus Request (input, active Low). This input is
used by external devices (such as DMA controllers) to
request access to the system bus. This request has a
higher priority than /NMI and is always recognized at the
end of the current machine cycle. This signal stops the
CPU from executing further instructions and places the
address and data buses, and other control signals, into the
High impedance state.
/NMI. Non-Maskable Interrupt (input, negative edge trig-
gered). /NMI has a higher priority than /INT and is always
recognized at the end of an instruction, regardless of the
state of the interrupt enable flip-flops. This signal forces
CPU execution to continue at location 0066H.
/INT0. Maskable Interrupt Request 0 (input/open-drain
output, active Low). This signal is generated by internal
and external I/O devices. External devices should also
drive this signal in an open-drain fashion. The CPU will
honor this request at the end of the current instruction cycle
as long as it is enabled, and the /NMI and /BUSREQ signals
are inactive. The CPU acknowledges this interrupt request
with an interrupt acknowledge cycle. During this cycle,
both the /M1 and /IORQ signals will become active.
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