Z80185 Datasheet, PDF (84/95 Pages) Zilog, Inc. – SMART PERIPHERAL CONTROLLERS

Zilog
Wait State Generation (WSG)
PRELIMINARY
Z80185/Z80195
SMART PERIPHERAL CONTROLLERS
The Memory Wait Insertion field of the DCNTL register
applies to all accesses to memory, and allows insertion of
0-3 wait states. In the Z80185, the WSG Chip Select
Register allows individual wait state control for the various
types and areas of memory.
WSG Chip Select Register (I/O Address %D8)
765 43210
1 11 1 1 11 1
Other Memory Wait Insertion
On-Chip ROM Wait Insertion
/ROMCS Wait Insertion
/RAMCS Wait Insertion
Bits 3-2. This field controls how many wait states are
inserted for accesses to on-chip ROM, and is encoded like
bits 7-6. Note: On-chip ROM should be fast enough to
support no-wait-state operation at the maximum specified
clock rate, but this field is included as a “hedge” against
difficulties in this area, as well as to provide timing compat-
ibility in unusual circumstances.
Bits 1-0. This field controls how many wait states are
inserted for accesses to external memory in which neither
/RAMCS nor /ROMCS is asserted, and is encoded the
same as bits 7-6.
All fields in this register Reset to 11. The 4-wait-state
feature is included to allow the use of commodity DRAMs
with a clock rate at, or near, the maximum.
Figure 86. WSG Chip Select Register
(I/O Address %D8)
Bits 7-6. This field controls how many wait states are
inserted for accesses to external memory in which /RAMCS
is asserted: 00 = none, 01 = 1, 10 = 2, 11 = 4 wait states.
Note that this facility, and the one in the DCNTL register,
both logically OR into the WAIT signal, to allow this register
full control of wait states. Bits 7-6 of DCNTL should be
programmed to 00.
Bits 5-4. This field controls how many wait states are
inserted for accesses to external memory in which /ROMCS
is asserted, and is encoded like bits 7-6.
84
DS971850301