Z80185 Datasheet, PDF (24/95 Pages) Zilog, Inc. – SMART PERIPHERAL CONTROLLERS

Zilog
PRELIMINARY
Z80185/Z80195
SMART PERIPHERAL CONTROLLERS
/INT1, /INT2. Maskable Interrupt Requests 1 and 2 inputs,
active Low). These signals are generated by external I/O
devices. The CPU will honor these requests at the end of
the current instruction cycle as long as the /NMI, /BUSREQ,
and /INT0 signals are inactive. The CPU will acknowledge
these interrupt requests with an interrupt acknowledge
cycle. Unlike the acknowledgment for /INT0 during this
cycle, neither the /M1 nor the /IORQ signals will become
active. These pins may be programmed to provide active
Low level, rising or falling edge interrupts. The level of the
external /INT1 and /INT2 pins may be read in the Interrupt
Edge Register.
/RFSH. Refresh (output, active Low, tri-state). /RFSH and
/MREQ active indicate that the current CPU machine cycle
and the contents of the address bus should be used for
refresh of dynamic memories. The low order eight bits of
the address bus (A7-A0) contain the refresh address.
Z80185 UART and CSIO Signals
CKA0/CKS. Asynchronous Clock 0 or Serial Clock (input/
output). An optional clock input or output for ASCI channel
0 or the Clocked Serial I/O Port.
/DCD0/CKA1. Data Carrier Detect 0 or Asynchronous
Clock 1 (input/output). A Low-active modem status input
for ASCI channel 0, or a clock input or output for ASCI
channel 1.
/RTS0/TxS. Request to Send 0 or Clocked Serial Transmit
Data (output). A programmable modem control output for
ASCI channel 0, or the serial output from the CSIO channel.
/CTS0/RxS. Clear to Send 0 or Clocked Serial Receive
Data (input). A Low-active modem control input for ASCI
channel 0, or the serial data input to the CSIO channel.
TXA0. Transmit Data 0 (output). This output transmits data
from ASCI channel 0.
RXA0. Receive Data 0 (input). This input receives data for
ASCI channel 0.
RXA1. Receive Data 1 (input). This input receives data for
ASCI channel 1.
Multiplexed Signal
TOUT//DREQ. Timer Out or External DMA Request (input
or output). This pin can be programmed to be either TOUT,
the High-active pulse output from PRT channel 1, or a Low-
active DMA Request input from an external peripheral.
Z80185 EMSCC Signals
TXD. Transmit Data (output). This output transmits serial
data at standard TTL levels.
RXD. Receive Data (input). This input receives serial data
at standard TTL levels.
/TRXC. Transmit/Receive Clock (input or output). This pin
functions under program control. /TRXC may supply the
receive clock or the transmit clock in the input mode or
supply the output of the digital phase-locked loop, the
crystal oscillator, the baud rate generator, or the transmit
clock in the output mode.
/RTXC. Receive/Transmit Clock (input). This pin functions
under program control. /RTXC may supply the receive
clock, the transmit clock, the clock for the baud rate
generator, or the clock for the digital phase-locked loop.
The receive clock may be 1, 16, 32, or 64 times the data
rate in asynchronous mode.
/CTS. Clear To Send (input, active Low). If this pin is
programmed as an “auto enable”, a Low on it enables the
EMSCC transmitter. If not programmed as an auto enable,
it can be used as a general-purpose input. This pin is
Schmitt-trigger buffered to accommodate slow rise-times.
The EMSCC detects transitions on this input and can
interrupt the processor on either logic level transition.
/DCD. Data Carrier Detect (input, active Low). This pin
functions as an EMSCC receiver enable when programmed
as an “auto enable”; otherwise it can be used as a general-
purpose input pin. The pin is Schmitt-trigger buffered to
accommodate slow rise-times. The EMSCC detects tran-
sitions on this pin and can interrupt the processor on either
logic level transition.
TXA1. Transmit Data 1 (output). This output transmits data
from ASCI Channel 1.
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