Z80185 Datasheet, PDF (68/95 Pages) Zilog, Inc. – SMART PERIPHERAL CONTROLLERS

Zilog
PRELIMINARY
Z80185/Z80195
SMART PERIPHERAL CONTROLLERS
A second output register has been added for PIA27-20.
Writing to either the Z80181-compatible PIA 2 Data Regis-
ter (address E3) or the new Alternate PIA 2 Data Register
(address EE) writes to the Output Holding Register (OHR).
When the PIA27-20 pins are outputs, the outputs of the
OHR are the inputs to the second register, which is called
the I/O register (IOR), these outputs drive the PIA27-20
pins. When the pins are inputs, they are the inputs to the
IOR, which can be read from the PIA 2 Data Register
(address E3).
In non-P1284 mode, Host Negotiation mode, Reserved
Modes, and in Peripheral Compatible/Negotiation mode
when the host drives nSelectIn (P1284Active) High to
select negotiation, the direction of the PIA27-20 pins are
controlled by the PIA 2 Data Direction register, as on the
Z80181. Also in these modes the IOR is loaded on every
PHI clock, so that operation is virtually identical to the
Z80181. In other modes the controller controls the direc-
tion of PIA27-20 and when the IOR is loaded.
A Time Constant Register PART must be loaded by soft-
ware with the smallest number of PHI clocks that equals
or exceeds the “critical time” for the mode selected in
PARM. The critical time is 750 ns for Host Compatible
mode, 500 ns for most other modes, and the time neces-
sary to indicate DMA completion in Host ECP Forward and
Peripheral ECP Reverse modes.
Set IUS clr IP clr IUS
number of PHI clocks in critical time
7
6
5
4
3
2
1
0
Figure 78. PART Write (I/O Address %DC)
Reading PART yields the status of the IP and IUS bits,
which are described in the Bidirectional Centronics Inter-
face section:
IUS
IP
0
number of PHI clocks in critical time
7
6
5
4
3
2
1
0
Figure 79. PART Read (I/O Address %DC)
The Vector Register PARV must be loaded by software with
the interrupt vector to be used for interrupts from this
controller.
Interrupt Vector
7
6
5
4
3
2
1
0
Figure 80. PARV (I/O Address %DD)
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