Z80185 Datasheet, PDF (37/95 Pages) Zilog, Inc. – SMART PERIPHERAL CONTROLLERS

Zilog
PRELIMINARY
Z8S180 MPU REGISTERS
ASCI CHANNELS CONTROL REGISTERS
Z80185/Z80195
SMART PERIPHERAL CONTROLLES
CNTLA0
Bit MPE RE
Upon RESET
R/W
0
0
R/W R/W
Addr 00H
TE
/RTS0
MPBR/
EFR
MOD2
MOD1
MOD0
0
1
x
0
0
0
R/W R/W R/W R/W R/W R/W
MODE Selection
0
0
0 Start + 7-Bit Data + 1 Stop
0
0
1 Start + 7-Bit Data + 2 Stop
0
1
0 Start + 7-Bit Data + Parity + 1 Stop
0
1
1 Start + 7-Bit Data + Parity + 2 Stop
1
0
0 Start + 8-Bit Data + 1 Stop
1
0
1 Start + 8-Bit Data + 2 Stop
1
1
0 Start + 8-Bit Data + Parity + 1 Stop
1
1
1 Start + 8-Bit Data + Parity + 2 Stop
Read - Multiprocessor Bit Receive
Write - Error Flag Reset
Request To Send
Transmit Enable
Receive Enable
Multiprocessor Enable
Figure 23a. ASCI Control Register A (Ch. 0)
CNTLA1
Bit MPE RE
Upon RESET
R/W
0
0
R/W R/W
TE
0
R/W
Addr 01H
CKA1D ^MPBR/ MOD2 MOD1 MOD0
EFR
1
x
0
0
0
R/W R/W R/W R/W R/W
MODE Selection
0
0
0 Start + 7-Bit Data + 1 Stop
0
0
1 Start + 7-Bit Data + 2 Stop
0
1
0 Start + 7-Bit Data + Parity + 1 Stop
0
1
1 Start + 7-Bit Data + Parity + 2 Stop
1
0
0 Start + 8-Bit Data + 1 Stop
1
0
1 Start + 8-Bit Data + 2 Stop
1
1
0 Start + 8-Bit Data + Parity + 1 Stop
1
1
1 Start + 8-Bit Data + Parity + 2 Stop
Read - Multiprocessor Bit Receive
Write - Error Flag Reset
CKA1 Disable
Transmit Enable
Receive Enable
Multiprocessor Enable
Figure 23b. ASCI Control Register A (Ch. 1)
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