Z80185 Datasheet, PDF (47/95 Pages) Zilog, Inc. – SMART PERIPHERAL CONTROLLERS

Zilog
DMA REGISTER DESCRIPTION
PRELIMINARY
Z80185/Z80195
SMART PERIPHERAL CONTROLLES
Bit 7. This bit should be set to 1 only when both DMA
channels are set to take their requests from the same
device. If this bit is 1 (it resets to 0), the channel end output
of DMA channel 0 sets a flip-flop, so that thereafter the
device’s request is visible to channel 1, but is not visible to
channel 0. The channel end output of channel 1 clears the
FF, so that thereafter, the device’s request is visible to
channel 0, but not visible to channel 1.
Bit 6. When both DMA channels are programmed to take
their requests from the same device, this bit (FF mentioned
in the previous paragraph) controls which channel the
device’s request is presented to: 0 = DMA 0, 1 = channel
1. When bit 7 is 1, this bit is automatically toggled by the
channel end output of the channels, as described above.
Bits 5-4. Reserved and should be programmed as 0.
Bits 3. This bit controls the direction and use of the TOUT/
DREQ pin. When it’s 0, TOUT/DREQ is the DREQ input;
when it’s 1, TOUT/DREQ is an output that can carry the
TOUT signal from PRT1, if PRT1 is so programmed.
IAR1L
Read/Write
IA7
Addr 2BH
IA0
Bits 2-0. With “DIM1”, bit 1 of DCNTL, these bits control
which request is presented to DMA channel 1, as follows:
DIM1 IAR18-16 Request Routed to DMA Channel 1
0
000
0
001
0
010
0
011
0
10X
0
1X0
0
111
ext TOUT/DREQ
ASCI0 Tx
ASCI1 Tx
EMSCC out
Reserved, do not program.
Reserved, do not program.
PIA27-20 out
1
000
1
001
1
010
1
011
1
10X
1
1X0
1
111
ext TOUT/DREQ
ASCI0 Rx
ASCI1 Rx or TOUT//DREQ pin
EMSCC in
Reserved, do not program.
Reserved, do not program.
PIA27-20 in
BCR1L
Read/Write
BC7
Addr 2EH
BC0
IAR1H
Read/Write
IA15
Addr 2CH
IA8
BCR1H
Read/Write
BC15
Addr 2FH
BC8
Figure 52. DMA I/O Address Registers
Figure 53. DMA 1 Byte Count Registers
Bit
Upon Reset
R/W
DSTAT
DE1
0
R/W
DE0 /DWE1 /DWE0 DIE1
0
1
1
0
R/W W W R/W
DIE0
0
R/W
Addr 30H
- DIME
10
R
DMA Master Enable
DMA Interrupt Enable 1, 0
DMA Enable Bit Write Enable 1, 0
DMA Enable Ch 1, 0
Figure 54. DMA Status Register
DS971850301
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