Z80185 Datasheet, PDF (71/95 Pages) Zilog, Inc. – SMART PERIPHERAL CONTROLLERS

Zilog
PRELIMINARY
Z80185/Z80195
SMART PERIPHERAL CONTROLLES
Z80185 BIDIRECTIONAL CENTRONICS P1284 CONTROLLER (Continued)
Host Compatible Mode
Host Negotiation Mode
1. Setting this mode configures PIA27-20 as outputs re-
gardless of the contents of register E2. When entering
this mode, the controller sets the Idle and DREQ bits,
but these settings do not request an interrupt.
2. If software, or a DMA channel, writes eight bits to the
Output Holding Register (OHR) when Idle is set, the
controller transfers the byte to the Input/Output Regis-
ter and negates DREQ only momentarily, so as to
request another byte from software or the DMA chan-
nel.
3. In this mode, the nAutoFd line is not under control of the
PARC register, but rather under control of which regis-
ter the software uses to write data to the OHR. Each time
the controller transfers a byte from the OHR to the Input/
Output Register, it sets nAutoFd High if the byte was
written to address E3, and Low if the byte was written to
the “alternate” address EE. In a DMA application all of
the bytes transferred from one output buffer will have
the same state of nAutoFd, but this state can be
changed from one buffer to the next by changing the
I/O address used by the DMA channel. In non-DMA
applications software can set the state of nAutoFd for
each character, by writing data to the two different
register addresses.
4. When a data byte has been valid on PIA27-20 for 750
ns (as controlled by the PART register), and the Busy
and PError lines are Low and the Select, nAck, and
nFault lines are High, the controller drives nStrobe Low.
After the controller has held nStrobe Low for 750 ns it
drives nStrobe back to High. Then it waits for 750 ns of
data hold time to elapse. If software or a DMA channel
has written another byte to the Output Holding Register
(thus clearing DREQ) by the time this wait is satisfied,
the controller transfers the byte from the Output Holding
Register to the Input/Output Register, sets DREQ again,
and returns to the event sequence at the start of this
paragraph. Otherwise, it sets Idle and returns to the
event sequence at the start of paragraph #2.
Status interrupts in this mode include rising and falling
edges on PError, nFault, and Select.
Setting this mode puts PIA27-20 under control of registers
E2 and E3, as on the Z80181.
Software has complete control of the controller, and can
either revert to Host Compatibility mode, or set one of the
following Host modes, depending on how the peripheral
responds to the Negotiation value(s).
Status interrupts in this mode include rising and falling
edges on PtrClk (nAck), nAckReverse (PError), and
nPeriphRequest (nFault). nFault is not used during actual
P1284 negotiation, but is included because these events
are significant during Byte and ECP mode idle times.
Host Reserved Mode
This mode differs from Host Negotiation mode only in that
there are no status interrupts in this mode.
Peripheral Compatible/Negotiation Mode
In this mode, if P1284Active (nSelectIn) is Low, the control-
ler sets PIA27-20 as inputs, regardless of the contents of
register E2; when P1284Active (nSelectIn) is High, PIA27-
20 are under the control of registers E2 and E3. On entry
to this mode, the controller sets the Idle bit, if DREQ is set
from a previous mode.
If, in this mode, nStrobe goes (is) Low, P1284Active
(nSelectIn) is Low, and DREQ is 0, indicating that any
previous data has been taken by the processor or DMA
channel, the controller captures the data on PIA27-20 into
the Input/Output Register, sets DREQ to notify software or
the DMA channel to take the byte, drives the Busy line
High, and one PHI clock later drives nAck Low. When at
least 500 ns (as controlled by the PART register) have
elapsed, the controller drives nAck back to High. One PHI
clock later, if the CPU or DMA has taken the data and thus
cleared DREQ, the controller drives Busy back to Low,
otherwise it sets Idle.
Select, PError and nFault are under software control in this
mode, and nAutoFd can be sensed by software, but has no
other effect on operation.
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