Z80185 Datasheet, PDF (44/95 Pages) Zilog, Inc. – SMART PERIPHERAL CONTROLLERS

Zilog
TIMER CONTROL REGISTER
PRELIMINARY
Z80185/Z80195
SMART PERIPHERAL CONTROLLERS
Bit
Upon Reset
R/W
TCR
TIF1
0
R
TIF0
0
R
Addr 10H
TIE1 TIE0 TOC1 TOC0 TDE1 TDE0
0 0 0 00 0
R/W R/W R/W R/W R/W R/W
Timer Down Count Enable 1,0
Timer Output Control 1,0
Timer Interrupt Enable 1,0
Timer Interrupt Flag 1,0
TOC1,0 A15/TOUT
00 Inhibited
01
Toggle
10
0
11
1
Figure 44. Timer Control Register
FREE RUNNING COUNTER
FRC
Read Only
Addr 18H
76 543 210
Figure 45. Free Running Counter
CPU CONTROL REGISTER
CPU Control Register (CCR) Addr 1FH
D7 D6 D5 D4 D3 D2 D1 D0
000 00 000
Figure 46. CPU Control Register
Note: See Figure 87 for full description.
44
DS971850301