Z80185 Datasheet, PDF (16/95 Pages) Zilog, Inc. – SMART PERIPHERAL CONTROLLERS

Zilog
PRELIMINARY
I/O Port Timing
No. Symbol
Parameter
Z80185 / Z80195
(20 MHz)
Min Max
A1 TdWR (PIA) Data Valid Delay from WR Rise
60
Z80185/Z80195
SMART PERIPHERAL CONTROLLERS
Z80185 / Z80195
(33 MHz)
Min Max Units
60 ns
External Bus Master Timing
No. Symbol
B1 TsA(wf)
(rf)
B2 TsIO(wf)
(rf)
B3 Th
B4 TdRD(DO)
B5 TdRIr(DOz)
B6 TsDI(WRf)
B7 TsA(IORQf)
B8 TsA(RDf)
B9 TsA(WRf)
Parameter
Address Valid to WR or
RD Fall Time
IORQ Fall to WR or
RD Fall Time
Data Hold Time (from WR Rise)
RD Fall to Data Out Delay
RD,IORQ Rise to Data Float Time
Data In to WR Fall Setup Time
Address to IORQ Fall Setup Time
Address to RD Fall Setup Time
Address to WR Fall Setup Time
Z80185 / Z80195
(20 MHz)
Min Max
Z80185 / Z80195
(33 MHz)
Min Max Units
40
40
ns
20
20
ns
5
5
ns
35
35
ns
5
5
ns
20
20
ns
20
20
ns
40
40
ns
40
40
ns
16
DS971850301