Z80185 Datasheet, PDF (29/95 Pages) Zilog, Inc. – SMART PERIPHERAL CONTROLLERS

Zilog
PRELIMINARY
Z80185/Z80195
SMART PERIPHERAL CONTROLLES
Z80185 MPU FUNCTIONAL DESCRIPTION (Continued)
DMA Controller
The two DMA channels of the Z80185 can transfer data to
or from the EMSCC channel, the parallel interface, the
async ports, or an external device. The I/O device encod-
ing in SAR18-16 and DAR18-16 of the existing Z80180 is
modified as shown in Table 1.
DMA request signals between the various cells are handled
internally by the mechanisms described in this section,
and are not pinned-out, nor are the TEND termination
count outputs of the DMA channels.
SM1-0
11
11
11
11
11
11
11
SAR18-16
000
001
010
011
10X
1X0
111
Table 1. SAR18-16 and DAR18-16 I/O Device Encoding
Source
DM1-0 DAR18-16
Destination
ext (TOUT/DREQ)
11
ASCI0 Rx
11
ASCI1 Rx
11
EMSCC Rx
11
Reserved, do not program.
11
11
PIA27-20 in
11
000
ext (TOUT/DREQ)
001
ASCI0 Tx
010
ASCI1 Tx
011
EMSCC Tx
10X
Reserved, do not program.
1X0
111
PIA27-20 out
Asynchronous Serial Communications
Interface (ASCI)
The ASCI logic provides two individual full-duplex UARTs.
Each channel includes a programmable baud rate gen-
erator and modem control signals. The ASCI channels can
also support a multiprocessor communications format. For
ASCI0, up to three modem control signals and one clock
signal can be pinned out, while ASCI1 has a data-only
interface.
The receiver includes a 4-byte FIFO, plus a shift register as
shown in Figure 22.
During Reset and in I/O Stop state, and for ASCI0 if /DCD0
is auto-enabled and is High, an ASCI is forced to the
following conditions:
s FIFO Empty
s All Error Bits Cleared (including those in the FIFO)
s Receive Enable Cleared (cntla bit 6 = 0)
s Transmit Enable Cleared (cntla bit 5 = 0).
If DCD is not auto-enabled, the /DCD pin has no effect on
the FIFOs or enable bits.
Overrun
Error
Error
Latches
4x4 Bit
Error
FIFO
PFOB
EERK
MP
Bit
4-Byte
Data FIFO
Notes:
PE = Parity Error
FE = Framing Error
OR = Overrun
BK = Break
MP = Multiprocessor Bit
Error
Shift Register
RXA
Figure 22. ASCI Receiver
DS971850301
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