Z80185 Datasheet, PDF (36/95 Pages) Zilog, Inc. – SMART PERIPHERAL CONTROLLERS

Zilog
PRELIMINARY
Z8S180 MPU REGISTER MAP
Notes:
Registers listed in boldface type represent new registers added to the Z8S180.
All register addresses not listed are Reserved.
Z80185/Z80195
SMART PERIPHERAL CONTROLLERS
Register Name
ASCI Control Register A Ch 0
ASCI Control Register A Ch 1
ASCI Control Register B Ch 0
ASCI Control Register B Ch 1
ASCI Status Register Ch 0
ASCI Status Register Ch 1
ASCI TX Data Register Ch 0
ASCI TX Data Register Ch 1
ASCI RX Data Register Ch 0
ASCI RX Data Register Ch 1
CSIO Control Register
CSIO Transmit/Receive Data Reg.
Timer Data Register Ch OL
Timer Data Register Ch OH
Reload Register Ch OL
Reload Register Ch OH
Timer Control Register
ASCI0 Extension Control Reg.
ASCI1 Extension Control Reg.
Timer Data Register Ch 1L
Timer Data Register Ch 1H
Timer Reload Register Ch 1L
Timer Reload Register Ch 1H
Free Running Counter
ASCI0 Time Constant Low
ASCI0 Time Constant High
ASCI1 Time Constant Low
ASCI1 Time Constant High
I/O Addr/Access
%0000/40/80 R/W
%0001/41/81 R/W
%0002/42/82 R/W
%0003/43/83 R/W
%0004/44/84 R/W
%0005/45/85 R/W
%0006/46/86 R/W
%0007/47/87 R/W
%0008/48/88 R/W
%0009/49/89 R/W
%000A/4A/8A R/W
%000B/4B/8B R/W
%000C/4C/8C R/W
%000D/4D/8D R/W
%000E/4E/8E R/W
%000F/4F/8F R/W
%0010/50/90
%0012/52/92 R/W
%0013/53/93 R/W
%0014/54/94 R/W
%0015/55/95 R/W
%0016/56/96 R/W
%0017/57/97 R/W
%0018/58/98 R/W
%001A/5A/9A R/W
%001B/5B/9B R/W
%001C/5C/9C R/W
%001D/5D/9D RW
Register Name
I/O Addr/Access
CPU Control Register
DMA Source Addr Register Ch OL
DMA Source Addr Register Ch OH
DMA Source Addr Register Ch OB
DMA Dest Addr Register Ch OL
DMA Dest Addr Register Ch OH
DMA Dest Addr Register Ch OB
DMA Byte Count Register Ch OL
DMA Byte Count Register Ch OH
DMA Memory Addr Register Ch 1L
DMA Memory Addr Register Ch 1H
DMA Memory Addr Register Ch 1B
DMA I/O Addr Register Ch 1L
DMA I/O Addr Register Ch 1H
DMA I/O Addr Register Ch 1B
DMA Byte Count Register Ch 1L
DMA Byte Count Register Ch 1H
DMA Status Register
DMA Mode Register
DMA/WAIT Control Register
IL Register
INT/TRAP Control Register
Refresh Control Register
MMU Common Base Register
MMU Bank Base Register
MMU Common/Bank Area Register
Operation Mode Control Register
I/O Control Register
%001F/5F/9F R/W
%0020/60/A0 R/W
%0021/61/A1 R/W
%0022/62/A2 R/W
%0023/63/A3 R/W
%0024/64/A4 R/W
%0025/65/A5 R/W
%0026/66/A6 R/W
%0027/67/A7 R/W
%0028/68/A8 R/W
%0029/69/A9 R/W
%002A/6A/AA R/W
%002B/6B/AB R/W
%002C/6C/AC R/W
%002D/6D/AD R/W
%002E/6E/AE R/W
%002F/6F/AF R/W
%0030/70/B0 R/W
%0031/71/B1 R/W
%0032/72/B2 R/W
%0033/73/B3 R/W
%0034/74/B4 R/W
%0036/76/B6 R/W
%0038/78/B8 R/W
%0039/79/B9 R/W
%003A/7A/BA R/W
%003E/7E/BE R/W
%003F/7F/BF R/W
36
DS971850301