Z80185 Datasheet, PDF (49/95 Pages) Zilog, Inc. – SMART PERIPHERAL CONTROLLERS

Zilog
PRELIMINARY
DMA REGISTERS (Continued)
Bit
Upon Reset
R/W
DCNTL
MWI1 MWI0 IWI1
1
1
1
R/W R/W R/W
IWI0
1
R/W
Addr 32H
DMS1 DMS0 DIM1 DIM0
0
0
0
0
R/W R/W R/W R/W
Z80185/Z80195
SMART PERIPHERAL CONTROLLES
DMA Ch 1 I/O Memory
Mode Select
/DREQi Select, i = 1, 0
I/0 Wait Insertion
Memory Wait Insertion
* _{MWI1, 0 No. of Wait States}
00
0
01
1
10
2
11
3
IWI1, 0
00
01
10
11
No. of Wait States
1
2
3
4
DMSi
1
0
Sense
Edge Sense
Level Sense
DM1, 0
Transfer Mode
Address Increment/Decrement
00
M - I/O
MAR1+1
IAR1 Fixed
01
M - I/O
MAR1-1
IAR1 Fixed
10
I/O - M
IAR1 Fixed
MAR1+1
11
I/O - M
IAR1 Fixed
MAR1-1
Note:
* If using the Wait-State Generators provided in
register D8, the MWI1-0 bits should be set to 00.
Figure 56. DMA/WAIT Control Register
DS971850301
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