Z80185 Datasheet, PDF (70/95 Pages) Zilog, Inc. – SMART PERIPHERAL CONTROLLERS

Zilog
Interrupts
PRELIMINARY
Z80185/Z80195
SMART PERIPHERAL CONTROLLERS
As in other Zilog peripherals, the controller includes an
interrupt pending bit (IP), and an interrupt under service bit
(IUS). The controller is part of an on-chip interrupt acknowl-
edge daisy-chain that extends from the IEI pin, through the
EMSCC, CTC, and this controller in a programmable
priority order, and from the lowest-priority of these devices
to the IEO pin. The interrupt request from the controller is
logically ORed with /INT0 and other on-chip interrupt
requests to the processor.
The controller sets its IP bit whenever any of three condi-
tions occurs:
1. PARM4 is 1, and the controller sets the DREQ bit. This
does not include when the controller forces the DREQ
bit to 1, when software first places the controller in
Peripheral Nibble, Peripheral Byte, Peripheral ECP
Reverse, Host Compatible, or Host ECP Forward mode.
2. PARM5 is 1, and a mode-dependent “status interrupt”
condition occurs. The following sections describe the
status interrupt conditions (if any) for each mode.
3. PARM6 is 1, and the controller sets the Idle bit, except
when the controller forces the Idle bit to 1, when
software first places the controller in Peripheral Nibble,
Peripheral Byte, Peripheral ECP Reverse, Host Com-
patible, or Host ECP Forward mode. The following
sections describe when Idle is set in each mode.
Once IP is set, it remains set until software writes a 1 to
PART6.
The controller will begin requesting an interrupt of the
processor whenever IP is set, its IEI signal from the on-chip
daisy-chain is High/true, and its IUS bit is 0. Once it starts
requesting an interrupt, the controller will continue to do so
until /IORQ goes Low in an interrupt-acknowledge cycle,
or IP is 0, or IUS is 1.
The controller drives its IEO output High, if its IEI input is
High, and its IP and IUS bits are both 0. A Z80 interrupt
acknowledge cycle is signalled by /M1 going Low, fol-
lowed by /IORQ going Low. The controller, and all other
devices in the daisy-chain, freeze the contribution of their
IP bits to their IEO outputs while /M1 is Low, which prevents
new events from affecting the daisy-chain. By the time
/IORQ goes Low, one and only one device will have its IEI
pin High and its IEO pin Low — this device responds to the
interrupt by providing an interrupt vector, and setting its
IUS bit. This controller also clears its IP bit when it responds
to an interrupt acknowledge cycle.
The interrupt service routine, that is initiated when the
interrupt vector value identifies an interrupt from this con-
troller, should save the processor context and then pro-
ceed as follows:
1. If the ISR does not allow nested interrupts, it can clear
the IP and IUS bits by writing hex 60, plus the “critical
time” value to the PART, then read the status from PARC
and proceed based on that status. Near the end of the
ISR it should re-enable processor interrupts.
2. If the ISR allows nested interrupts, it can re-enable
processor interrupts, clear IP by writing hex 40 plus the
“critical time” value to the PART, and then read the
status from PARC and proceed based on that status. At
the end of the ISR it should clear IUS to allow further
interrupts from this controller and devices lower on the
daisy-chain, by writing hex 20 plus the “critical time”
value to the PART.
The remainder of this section describes the operation of
the various PARM register modes that can be selected.
Non-P1284 Mode
The Z80185 defaults to this mode after a Reset, and this
mode is compatible with the use of PIA27-20 on the
Z80181. The directions of PIA27-20 can be controlled
individually by writing to register E2, as on the Z80181. The
state of outputs among PIA27-20 can be set by writing to
register E3, and the state of all eight pins can be sensed by
reading register E3. The Busy, nAck, PError, nFault, and
Select pins are tri-stated in this mode, while nStrobe,
nAutoFd, nSelectIn, and nInit are inputs. There are no
status interrupts in this mode.
Peripheral Inactive Mode
This mode operates identically to Non-P1284 mode as
described above, except that the Busy, nAck, PError,
nFault, and Select pins are outputs that can be controlled
via the PARC and PARC2 registers, and status interrupts
can occur in response to any edge on nAutoFd, nStrobe,
nSelectIn, or nInit. This mode differs from Peripheral Com-
patibility/Negotiation mode with nSelectIn (P1284 Active)
High, only in that the controller will not operate in Compat-
ibility mode if nSelectIn goes Low.
70
DS971850301