Z80185 Datasheet, PDF (34/95 Pages) Zilog, Inc. – SMART PERIPHERAL CONTROLLERS

Zilog
PRELIMINARY
STANDBY Mode Exit with BUS REQUEST
Z80185/Z80195
SMART PERIPHERAL CONTROLLERS
Optionally, if the BREXT bit (D5 of CPU Control Register) is
set to 1, the Z8S180 exits STANDBY mode when the
/BUSREQ input is asserted; the crystal oscillator is then
restarted. An internal counter automatically provides time
for the oscillator to stabilize, before the internal clocking
and the system clock output of the Z8S180 are resumed.
1. Exit with Non-Maskable Interrupts
If /NMI is asserted, the CPU begins a normal NMI interrupt
acknowledge sequence after clocking resumes.
2. Exit with External Maskable Interrupts
The Z8S180 relinquishes the system bus after the clocking
is resumed by:
s Tri-State the address outputs A19 through A0.
s Tri-State the bus control outputs /MREQ, /IORQ,
/RD and /WR.
s Asserting /BUSACK
The Z8S180 regains the system bus when /BUSREQ is
deactivated. The address outputs and the bus control
outputs are then driven High; the STANDBY mode is
exited.
If the BREXT bit of the CPU Control Register (CCR) is
cleared, asserting the /BUSREQ will not cause the Z8S180
to exit STANDBY mode.
If STANDBY mode is exited due to a reset or an external
interrupt, the Z8S180 remains relinquished from the sys-
tem bus as long as /BUSREQ is active.
STANDBY Mode Exit with External Interrupts
STANDBY mode can be exited by asserting input /NMI.
The STANDBY mode may also exit by asserting /INT0,
/INT1 or /INT2, depending on the conditions specified in
the following paragraphs.
/INT0 wake-up requires assertion throughout duration of
clock stabilization time (2¹⁷ clocks).
If exit conditions are met, the internal counter provides time
for the crystal oscillator to stabilize, before the internal
clocking and the system clock output within the Z8S180
are resumed.
If an External Maskable Interrupt input is asserted, the CPU
responds according to the status of the Global Interrupt
Enable Flag IEF1 (determined by the ITE1 bit) and the
settings of the corresponding interrupt enable bit in the
Interrupt/Trap Control Register (ITC: I/O Address = 34H):
a. If an interrupt source is disabled in the ITC, asserting
the corresponding interrupt input will not cause the
Z8S180 to exit STANDBY mode. This is true regardless
of the state of the Global Interrupt Enable Flag IEF1.
b. If the Global Interrupt Flag IEF1 is set to 1, and if an
interrupt source is enabled in the ITC, asserting the
corresponding interrupt input causes the Z8S180 to
exit STANDBY mode. The CPU performs an interrupt
acknowledge sequence appropriate to the input be-
ing asserted when clocking is resumed if:
s The interrupt input follows the normal
interrupt daisy-chain protocol.
s The interrupt source is active until the
acknowledge cycle is completed.
c. If the Global Interrupt Flag IEF1 is disabled, in other
words, reset to 0, and if an interrupt source is enabled
in the ITC, asserting the corresponding interrupt input
will still cause the Z8S180 to exit STANDBY mode. The
CPU will proceed to fetch and execute instructions
that follow the SLEEP instruction when clocking is
resumed.
If the External Maskable Interrupt input is not active until
clocking resumes, the Z8S180 will not exit STANDBY
mode. If the Non-Maskable Interrupt (/NMI) is not active
until clocking resumes, the Z8S180 still exits the STANDBY
mode even if the interrupt sources go away before the
timer times out, because /NMI is edge-triggered. The
condition is latched internally once /NMI is asserted Low.
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