Z80185 Datasheet, PDF (40/95 Pages) Zilog, Inc. – SMART PERIPHERAL CONTROLLERS

Zilog
PRELIMINARY
STAT0
Bit RDRF OVRN PE
Upon Reset
0
0
0
R/W
R
R
R
Addr 04H
FE RIE /DCD0 TDRE TIE
0
0
† †† 0
R R/W R
R R/W
Z80185/Z80195
SMART PERIPHERAL CONTROLLERS
Transmit Interrupt Enable
Transmit Data Register
Empty
Data Carrier Detect
Receive Interrupt Enable
Framing Error
Parity Error
Over Run Error
Receive Data Register Full
† /DCD0 - Depending on the condition of /DCD0 Pin.
†† /CTS0 Pin TDRE
L
1
H
0
Figure 26. ASCI Status Register (Ch. 0)
STAT1
Addr 05H
Bit RDRF OVRN PE FE RIE CTS1E TDRE TIE
Upon Reset
0
0
0
00
0
1
0
R/W
R
R
R
R R/W R/W R R/W
Transmit Interrupt Enable
Transmit Data Register
Empty
Reserved
Receive Interrupt Enable
Framing Error
Parity Error
Over Run Error
Receive Data Register Full
Figure 27. ASCI Status Register (Ch. 1)
40
DS971850301