Z80185 Datasheet, PDF(72/95 Page) Zilog, Inc. – SMART PERIPHERAL CONTROLLERS

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Z80185 Datasheet, PDF (72/95 Pages) Zilog, Inc. – SMART PERIPHERAL CONTROLLERS

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Zilog

PRELIMINARY

Z80185/Z80195

SMART PERIPHERAL CONTROLLERS

In this mode, software should monitor for the condition

P1284Active (nSelectIn) High, and nAutoFd Low simulta-

neously. If software detects this state, it should participate

in a Negotiation process. Software should read the value

on PIA27-20 and set PError, nFault, XFlag, and nAck as

appropriate for the data value. As long as P1284Active

(nSelectIn) remains High in this mode, software is in

complete control of the controller. After the host has driven

nStrobe Low and then High again for an acceptable value,

software should reprogram the MODE field to the appropri-

ate one of the following Peripheral modes.

Status interrupts in this mode include rising and falling

edges on P1284Active (nSelectIn) and nInit, and rising

and falling edges on HostBusy (nAutoFd) and HostClk

(nStrobe) while P1284Active (nSelectIn) is High.

Host Nibble Mode

1. If, during Host Negotiation mode, software has placed

the value 00 or 04 on the data lines, and received a

positive response on Xflag (Select) and a Low on

nDataAvail (nFault) at a rising edge of PtrClk (nAck),

then after optionally programming a DMA channel to

store data, it should set this mode.

2. For each byte in this mode, the controller drives HostBusy

(nAutoFd) Low and waits until DREQ is cleared, indicat-

ing that the CPU or DMA has taken any previous data,

and the peripheral has driven PtrClk (nAck) Low. At this

point it samples the other four status lines from the

peripheral into the less-significant four bits of the Input/

Output Register as follows:

The controller then drives HostBusy (nAutoFd) back to

High, and waits for the peripheral to drive PtrClk (nAck)

back to High. Then it drives HostBusy (nAutoFd) back

to Low and waits for the peripheral to drive PtrClk (nAck)

Low. At this point it samples the four status lines from the

peripheral into the most-significant four bits of the Input/

Output Register, as shown above. Then it drives

HostBusy (nAutoFd) back to High, sets the DREQ bit,

and waits for the peripheral to drive PtrClk (nAck) back

to High. When this occurs, if the peripheral is driving

nDataAvail (nFault) Low, indicating more data is avail-

able, the controller then returns to the event sequence

at the start of paragraph #2.

3. If nDataAvail (nFault) is High at a rising edge of nAck in

this mode, indicating that the peripheral has no more

data, the controller sets Idle and waits for software to

program it back to Host Negotiation mode. Software

can then select the next mode (reference IEEE P1284

specification).

If host software is programmed not to select all the data

that a peripheral has available, it should first disable the

DMA channel, if one is in use, then wait for DREQ to be 1

and PtrClk (nAck) to be High. If nDataAvail (nFault) is Low

at this point, the controller will have already driven HostBusy

(nAutoFd) Low to solicit the next byte. Software should

then program the controller back to Host Negotiation

mode, read the IOR to get the current byte, and take the

next byte from the peripheral under software control. After

the peripheral drives nAck High after the second nibble,

software can drive P1284Active (nSelectIn) Low to tell the

peripheral to leave Nibble mode.

Table 4. Nibble Mode Bit Assignments

Signal

First Data Bit

Second Data Bit

Busy

PError

Select

nFault

There are no status interrupts in Host Nibble mode.

DS971850301

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