Z80185 Datasheet, PDF (57/95 Pages) Zilog, Inc. – SMART PERIPHERAL CONTROLLERS

Zilog
PRELIMINARY
Z80185/Z80195
SMART PERIPHERAL CONTROLLES
EMSCC
The Z80185 features a one-channel EMSCC that uses two
I/O addresses:
EMSCC Channel A Control I/O Address %E8
Data I/O Address %E9
Divide-by-two should be programmed when operating the
Z80185 beyond 20 MHz, 5V.
Note: Upon power-up, or reset, the system clock is equal
to the EMSCC clock.
RR10, and RR15). Two registers (RR12 and RR13) are
read to learn the baud rate generator time constant. RR2
contains either the unmodified interrupt vector (channel A)
or the vector modified by status information (channel B).
RR3 contains the Interrupt Pending (IP) bits (channel A
only). RR6 and RR7 contain the information in the SDLC
Frame Status FIFO, but is only read when WR15 D2 is set.
If WR7' D6 is set, Write Registers WR3, WR4, WR5, WR7,
and WR10 can be read as RR9, RR4, RR5, and RR14,
respectively. Figure 51 shows the format of each read
register.
Initialization. The system program first issues a series of
commands to initialize the basic mode of operation. This is
followed by other commands to qualify conditions within
the selected mode. For example, in the Asynchronous
mode, character length, clock rate, number of stop bits,
and even or odd parity should be set first. Then the
interrupt mode is set, and finally, the receiver and transmit-
ter are enabled.
With the Z80185, the EMSCC channel's DTR, Tx and Rx
DMA Request and WAIT outputs are not subject to multi-
plexing and are routed separately to the CPU and pins.
In other words,
1. the DTR pin is not multiplexed and always follows WR5
bit 7;
Write Registers. The EMSCC contains 16 write registers
(17 counting the transmit buffer) in each channel. These
write registers are programmed separately to configure
the functional "personality" of the channels. A new register,
WR7', was added to the EMSCC and may be written to if
WR15, D0 is set. Figure 50 shows the format of each write
register.
Read Registers. The EMSCC contains ten read registers
(11 counting the receive buffer) in each channel. Four of
these may be read to obtain status information (RR0, RR1,
2. if WR1 bits 7-6 are 10, and the processor reads the RDR
when the RxFIFO is empty, or writes the TDR when the
TxFIFO is full, the processor is "waited" until a character
arrives or has been sent out;
3. WR1 bit 5 has no effect;
4. WR14 bit 2 should be kept 0;
5. WR1 bits 7-6 should not be programmed as 11.
DS971850301
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