Z80185 Datasheet, PDF (30/95 Pages) Zilog, Inc. – SMART PERIPHERAL CONTROLLERS

Zilog
FIFO and Receiver Operation
PRELIMINARY
Overrun Error
Z80185/Z80195
SMART PERIPHERAL CONTROLLERS
The 4-byte Receive FIFO is used to buffer incoming data
to reduce the incidence of overrun errors. When the RE bit
is set in the CNTLA register, the RXA pin is monitored for
a Low transition. One-half bit time after the Low transition
of the RXA pin, the ASCI samples RXA again. If it has gone
back to High, the ASCI ignores the previous Low transition
and resumes looking for a new one, but if RXA is still Low,
it considers this a start bit and proceeds to clock in the data
based upon the internal baud rate generator or the exter-
nal CKA pin. The number of data bits, parity, multiproces-
sor and stop bits are selected by the MOD2, MOD1, MOD0
and MP bits in the CNTLA and CNTLB registers. After the
data has been received the appropriate MP, parity and
one stop bit are checked. Data and any errors are clocked
into the FIFOs during the stop bit. Interrupts, Receive Data
Register Full Flag, and DMA requests will also go active
during this time.
Error Condition Handling
When the receiver places a data character in the Receive
FIFO, it also places any associated error conditions in the
error FIFO. The outputs of the error FIFO go to the set inputs
of the software-accessible error latches. Writing a 0 to
CNTLA EFR is the only way to clear these latches. In other
words, when an error bit reaches the top of the FIFO, it sets
an error latch. If the FIFO has more data and the software
reads the next byte out of the FIFO, the error latch remains
set, until the software writes a 0 to the EFR bit. The error bits
are cumulative, so if additional errors are in the FIFO, they
will set any unset error latches as they reach the top.
An overrun occurs if the receive FIFO is full when the
receiver has just assembled a byte in the shift register and
is ready to transfer it to the FIFO. If this occurs, the overrun
error bit associated with the previous byte in the FIFO is
set. The latest data byte is not transferred from the shift
register to the FIFO in this case, and is lost. Once an
overrun occurs, the receiver does not place any further
data in the FIFO, until the “last good byte received” has
come to the top of the FIFO so that the Overrun latch is set,
and software then clears the Overrun latch. Assembly of
bytes continues in the shift register, but this data is ignored
until the byte with the overrun error reaches the top of the
FIFO and is cleared with a write of 0 to the EFR bit.
Break Detect
A Break is defined as a framing error with the data equal to
all zeros. When a break occurs, the all-zero byte with its
associated error bits are transferred to the FIFO, if it is not
full. If the FIFO is full, an overrun is generated, but the
break, framing error and data, are not transferred to the
FIFO. Any time a break is detected, the receiver will not
receive any more data until the RXA pin returns to a High
state. If the channel is set in multiprocessor mode and the
MPE bit of the CNTLA register is set to 1, then breaks,
errors and data will be ignored unless the MP bit in the
transmission is a 1. Note: The two conditions listed above
could cause a break condition to be missed if the FIFO is
full and the break occurs, or if the MP bit in the transmission
is not a 1 with the conditions specified above.
Parity and Framing Errors
Parity and Framing Errors do not affect subsequent re-
ceiver operation.
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DS971850301