Z80185 Datasheet, PDF (6/95 Pages) Zilog, Inc. – SMART PERIPHERAL CONTROLLERS

Zilog
TIMING DIAGRAMS
Z8S180 MPU Timing
PRELIMINARY
Z80185/Z80195
SMART PERIPHERAL CONTROLLERS
Opcode Fetch Cycle
I/O Write Cycle †
I/O Read Cycle †
T1
T2
TW
T3
T1
T2
TW
T3
T1
5
4
2
3
ø
1
6
Address
/WAIT
20
20
19
19
11
7
12
/MREQ
/IORQ
/RD
/WR
/M1
8
9b
9a
14
7
29
11
28b
11
13
28a
13
9
11
22
25
26 and 26a
10
18
ST
Data
IN
Data
OUT
48
/RESET
54
17
15
16
15
23
24
49
48
54
53
Figure 4. CPU Timing
(Opcode Fetch Cycle, Memory Read/Write Cycle
I/O Read/Write Cycle)
16
21
27
49
53
6
DS971850301