Z80185 Datasheet, PDF (2/95 Pages) Zilog, Inc. – SMART PERIPHERAL CONTROLLERS

Zilog
TIMING DIAGRAMS (Continued)
PRELIMINARY
Processor
Power Controller
16-Bit Address Bus
8-Bit Data Bus
MMU
DMACs (2)
TxD,
RxD
EMSCC
Parallel Ports (2)
Including IEEE
Bidirectional
Centronics Controller
TOUT
16-Bit Programmable
Reload Timers (2)
UARTs (2)
Z80185/Z80195
SMART PERIPHERAL CONTROLLERS
Decode
A19-0
/ROMCS
/RAMCS
ROM
32K x 8
(Z80185 Only)
TXA1-0,
RXA1-0
CLK/TRG
CTCs (4)
ZC/TO
Figure 1. Z80185/195 Functional Block Diagram
2
DS971850301