Z80185 Datasheet, PDF (89/95 Pages) Zilog, Inc. – SMART PERIPHERAL CONTROLLERS

Zilog
PRELIMINARY
Z80185/Z80195
SMART PERIPHERAL CONTROLLES
Z80185 PIA AND MISCELLANEOUS REGISTERS (Continued)
CTC Control Registers (Continued)
Time Constant
Before a channel can start counting, it must receive a time
constant. The time constant value may be anywhere be-
tween 1 and 256, with 0 indicating a count of 256 (Figure
90).
D7 D6 D5 D4 D3 D2 D1 D0
TC0
TC1
TC2
TC3
TC4
TC5
TC6
TC7
Figure 90. CTC Time Constant
Interrupt Vector
If one or more of the CTC channels have interrupt enabled,
then the Interrupt Vector Word should be programmed.
Only the five most significant bits of this word are used, bit
D0 must be 0 . Bits D2-D1 are automatically modified by
the CTC channels after responding with an interrupt vector
(Figure 91).
D7 D6 D5 D4 D3 D2 D1 D0
0 Interrupt Vector Register
1 Control Register
Channel Identifier
(Automatically Inserted by CTC)
0 0 Channel 0
0 1 Channel 1
1 0 Channel 2
1 1 Channel 3
Supplied By User
Figure 91. CTC Interrupt Vector
Watch-Dog Timer
The Z80185's Watch-Dog Timer (WDT) facility is identical
to Zilog's Z84C15 WDT with the following exceptions:
1. The HALT mode field of the WDT Master Register is not
used. Power control is handled as on the Z8S180.
2. Rather than having a separate /WDTOUT output pin,
the output of the WDT is logically Low-active-ORed with
the /RESET pin. A new register bit controls whether this
affects only the processor, by means of an internal logic
gate, or whether it also drives the /RESET pin Low in an
open-drain manner, so that external logic can be Reset
by the WDT as well. The latter is the default state after
power-up or Reset.
DS971850301
89