Z80185 Datasheet, PDF (85/95 Pages) Zilog, Inc. – SMART PERIPHERAL CONTROLLERS

Zilog
PRELIMINARY
Z80185/Z80195
SMART PERIPHERAL CONTROLLES
Z80185 PIA AND MISCELLANEOUS REGISTERS (Continued)
Interrupt Edge Register
Interrupt Edge Register (I/O Address %DF)
7 65 4 321 0
0 10 1 0 00 0
0 = /DCD0/CKA0 is /DCD0
1 = /DCD0/CKA0 is CKA0
Drive Select for pins listed below
0 Select normal drive
1 Select low noise (33%)
drive capabilities
/INT1 Sense/Unlatch
0 in: /INT1 is low
1 in: /INT1 is high
out: unlatch edge detection
/INT2 Sense/Unlatch
0 in: /INT2 is low
1 in: /INT2 is high
out: unlatch edge detection
/INT1 Mode Select
0X Normal Level Detect
10 Falling (Neg) Edge Det.
11 Rising (Pos) Edge Det.
/INT2 Mode Select
0X Normal Level Detect
10 Falling (Neg) Edge Det.
11 Rising (Pos) Edge Det.
Figure 87. Interrupt Edge Register
(I/O Address %DF)
Bits 5-4. These bits control the interrupt capture logic for
the external /INT1 pin. When these bits are 0X, the /INT1 pin
is level sensitive and Low active. When these bits are 10,
negative edge detection is enabled. Any falling edge will
latch an active Low on the internal /INT1 to the processor.
This interrupt must be cleared by writing a 1 to bit 2 of this
register. Programming these bits to 11 enables rising edge
interrupts to be latched. The latch must be cleared in the
same fashion as for a falling edge.
Bit 3. Software can read this register to sense the state of
the /INT2 pin. Writing a 1 to this bit clears the edge
detection logic for /INT2.
Bit 2. Software can read this register to sense the state of
the /INT1 pin. Writing a 1 to this bit clears the edge
detection logic for /INT1.
Bit 1. This bit selects low noise or normal drive for the
parallel ports, bidirectional Centronics controller pins,
Chip Select pins, and EMSCC pins as follows:
PIA 10-13
PIA 14-16/ZCT0 0-2
PIA 27-20
/ROMCS
/RAMCS
/IOCS
IEO
/RTS
/DTR
TXD
/TRXC
BUSY
nAck
nAutoFd
nFault
nInit
nSelectIn
nStrobe
PError
Select
Bits 7-6. These bits control the interrupt capture logic for
the /INT2 pin. When these bits are 0X, the /INT2 pin is level
sensitive and Low active. When these bits are 10, negative
edge detection is enabled. Any falling edge will latch an
active Low on the internal /INT2 to the processor. This
interrupt must be cleared by writing a 1 to bit 3 of this
register. Programming these bits to 11 enables rising edge
interrupts to be latched. The latch must be cleared in the
same fashion as for a falling edge.
A 1 in this bit selects the low noise option, which is a 33
percent reduction in drive capability. A 0 selects normal
drive, and is the default after power-up. Additionally, refer
to CPU Register (CCR) for a list of the pins that are
programmable for low drive, via the CCR register.
Bit 0. If this bit is 1, the /DCD0/CKA1 pin has the CKA1
function. The pin is always connected to the DCD input of
ASCI0, so if this pin is 1, and ASCI0 is used, it should not
be programmed to use DCD as a receive auto-enable.
DS971850301
85