Z80185 Datasheet, PDF(74/95 Page) Zilog, Inc. – SMART PERIPHERAL CONTROLLERS

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Z80185 Datasheet, PDF (74/95 Pages) Zilog, Inc. – SMART PERIPHERAL CONTROLLERS

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Zilog

PRELIMINARY

Z80185/Z80195

SMART PERIPHERAL CONTROLLERS

In response to Idle, software should enter Host Negotiation

mode. Thereafter, it can set HostBusy (nAutoFd) Low, to

enter Reverse Idle state, or enter Host Compatible mode

(reference IEEE P1284 specification), or conduct a new

negotiation.

If software is programmed not to accept all the data that a

peripheral has available in this mode, it should first disable

the DMA channel, if one is in use, and then wait for DREQ

to be 1 and nAck to be 1. Then it should reprogram the

controller back to Host Negotiation mode, read the last

byte from the IOR, drive HostClk (nStrobe) back to High,

and then drive P1284Active (nSelectIn) Low to instruct the

peripheral to leave Byte mode.

There are no status interrupts in Host Byte mode.

Peripheral Byte Mode

1. Software should not set this mode until there is reverse

data available to send â that is, it should implement the

P1284 âreverse idle modeâ via software in Peripheral

Compatibility/Negotiation mode. The exact sequenc-

ing among PtrClk (nAck), nDataAvail (nFault), and

AckDataReq (PError) differs according to whether this

mode is entered directly from Negotiation or from

reverse idle phase, and is controlled by software. But in

either case, before software sets this mode, it should

set nDataAvail (nFault) and AckDataReq (PError) to

Low, then after 500 ns, set PtrClk (nAck) to High. When

it detects that the host has driven HostBusy (nAutoFd)

Low to request data, software should set this mode,

which sets the DREQ and Idle flags.

2. In this mode, as long as P1284Active (nSelectIn) re-

mains High, the controller drives PIA27-20 as outputs,

regardless of the contents of register E2. When soft-

ware, or a DMA channel, writes the first byte to the

Output Holding Register, the controller immediately

transfers the byte to the Input/Output Register, clears

Idle but negates DREQ only momentarily, to request

another byte from software, or the DMA channel.

3. After each byte is transferred to the IOR, the controller

waits 500 ns data setup time (as controlled by the PART

ter waits for the host to drive HostBusy (nAutoFd) High.

When this occurs, if software, or the DMA channel, has

not written more data to the Output Holding Register,

that is, if DREQ is still set, the controller sets the Idle flag

and waits for software or the DMA channel to do so. If

software, or the DMA channel, then writes data to the

Output Holding Register, the controller clears DREQ

and Idle. When there is data in the OHR and DREQ is 0,

this guarantees that it is appropriate to keep nDataAvail

(nFault), and AckDataReq (PError) Low to indicate that

more data is available, and the controller drives PtrClk

(nAck) back to High. The controller then waits for a

rising edge on HostClk (nStrobe), and then for the host

to drive HostBusy (nAutoFd) Low, at which time it

transfers the byte from the OHR to the Output Register,

sets DREQ, and then it returns to the event sequence at

the start of this paragraph.

While this mode is in effect, software should monitor the

interface for two conditions:

Case 1: Idle set and no more data to send, or

Case 2: P1284Active (nSelectIn) Low.

In Case #1, the software should write zero to register E3 to

keep PIA27-20 outputs momentarily, and then set the

mode back to Peripheral Compatibility, so that the inter-

face is fully under software control, set nDataAvail (nFault)

and AckDataReq (PError) High to signify no more data,

wait 500 ns, and set PtrClk (nAck) back to High. When

HostBusy goes back to Low, the software should set

PIA27-20 back to inputs.

In Case #2, if a falling edge on P1284Active happens any

time other than between a rising edge on HostClk (nStrobe),

and the next falling edge on HostBusy (nAutoFd), the

controller sets the IllOp bit to notify software that an

immediate Abort is in order, in which case software should

immediately enter Peripheral Compatibility/Negotiation

Mode. If P1284Active goes Low, but IllOp is not set,

meaning that the Host negated P1284Active in a âlegalâ

manner, software should enter Peripheral Inactive Mode

for the duration of the âreturn to Compatibility Modeâ, and

then enter Peripheral Compatibility/Negotiation Mode.

Status interrupts in Peripheral Byte Mode include rising

and falling edges on P1284Active (nSelectIn) and nInit.

DS971850301

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