Z80185 Datasheet, PDF (41/95 Pages) Zilog, Inc. – SMART PERIPHERAL CONTROLLERS

Zilog
PRELIMINARY
ASCI CHANNELS CONTROL REGISTERS (Continued)
Z80185/Z80195
SMART PERIPHERAL CONTROLLES
TDR0
Write Only
Addr 06H
7 6 5 4 32 1 0
Transmit Data
Figure 28. ASCI Transmit Data Register (Ch. 0)
TDR1
Write Only
Addr 07H
7 6 5 4 3 2 10
Transmit Data
Figure 29. ASCI Transmit Data Register (Ch. 1)
TSR0
Read Only
Addr 08H
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7 65 4 321 0
0 00 0 0 00 0
New Z8S180 Register
Send Break
0 = Normal Xmit
1 = Drive TXA Low
Break Detect (RO)
Break Feature Enable
BRG0 Mode
0 = As S180
1 = Enable 16-bit BRG counter
X1 bit clk ASCI0
0 = CKA0 /16 or /64
1 = CKA0 is bit clock
CTS0 Disable
0 = CTS0 Auto-Enable Tx
1 = CTS0 Advisory to SW
DCD0 Disable
0 = DCD0 Auto-Enables Rx
1 = DCD0 Advisory to SW
RDRF Interrupt Inhibit
Figure 32. ASCI0 Extension Control Register
(I/O Address 12)
Received Data
Figure 30. ASCI Receive Data Register (Ch. 0)
TSR1
Read Only
Addr 09H
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Received Data
Figure 31. ASCI Receive Data Register (Ch. 1)
7 65 4 321 0
0 00 0 0 00 0
New Z8S180 Register
Send Break
0 = Normal Xmit
1 = Drive TXA Low
Break Detect (RO)
Break Feature Enable
BRG1 Mode
0 = As S180
1 = Enable 16-bit BRG Counter
X1 Bit CLK ASCI1
0 = CKA1 /16 or /64
1 = CKA1 is bit Clock
Reserved (Program as 0)
RDRF Interrupt Inhibit
Figure 33. ASCI1 Extension Control Register
(I/O Address 13)
DS971850301
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