Z80185 Datasheet, PDF (52/95 Pages) Zilog, Inc. – SMART PERIPHERAL CONTROLLERS

Zilog
PRELIMINARY
Z80185/Z80195
SMART PERIPHERAL CONTROLLERS
SYSTEM CONTROL REGISTERS
OMCR
Addr 3EH
Bit M1E /M1TE /IOC ^-
-
-
-
-
Upon Reset 1
11
11 111
R/W ^{R/W W R/W}
I/O Compatibility
/M1 Temporary Enable
Notes:
1. This register should be programmed to 0x0xxxxxb
(x = don't care) as a part of Initialization.
2. If the M1E bit is set to 1, the processor does not
fetch a RETI instruction.
/M1 Enable
Figure 63. Operation Mode Control Register
ICR
Addr 3FH
Bit IOA7 IOA6 IOSTP ^-
-
-
-
-
Upon Reset 0
0
0
1
1
1
1
1
R/W ^{R/W R/W R/W}
I/O Stop
I/O Address
Combination of 11
is reserved
Figure 64. I/O Control Register
52
DS971850301