Z80185 Datasheet, PDF (26/95 Pages) Zilog, Inc. – SMART PERIPHERAL CONTROLLERS

Zilog
PRELIMINARY
Z80185/Z80195
SMART PERIPHERAL CONTROLLERS
System Control Signals
ST. Status (output, active High). This signal is used with the
/M1 and /HALT output to indicate the nature of each CPU
machine cycle.
/RESET. Reset Signal (input, active Low). /RESET signal is
used for initializing the Z80185 and other devices in the
system. It must be kept Low for at least three system clock
cycles.
IEI. Interrupt Enable Signal (input, active High). IEI is used
with IEO to form a priority daisy-chain when there are
external interrupt-driven Z80-compatible peripherals.
IEO. Interrupt Enable Output Signal (output, active High).
In an interrupt daisy-chain, IEO controls the interrupt of
external peripherals. IEO is active when IEI is 1 and the
CPU is not servicing an interrupt from the on-chip periph-
erals.
/IOCS. /IOCS decodes /IORQ, /M1, and as many address
lines as are necessary to ensure it is activated for an I/O
space access to any register in any block of eight registers
that does not contain any on-chip registers. Also included
in the decode is any programmed relocation of the “180
register set” in the ICR, and the “Decode High I/O” bit in the
System Configuration Register. If the “180 registers” aren’t
relocated, and “Decode High I/O” is 0, /IOCS is active from
address XX40 though XXD7, XXF8 through XXFF, and
NN00 through NN3F, where NN are non-zero. If the “180
registers” are not relocated and “Decode High I/O” is 1,
/IOCS is active from 0040 through 00D7, and 00F8 through
FFFF. /IOCS is active when an external master is in control
of the bus, as well as when the Z80185 processor has
control.
/RAMCS. RAM Chip Select (output, active Low). This
signal is driven Low for memory accesses at addresses
that fall between the values programmed into the RAMLBR
and RAMUBR registers. It is active when an external
master has control of the bus, as well as when the Z80185
processor is in control.
/ROMCS. ROM Chip Select (output, active Low). This
output is driven Low for memory accesses between the top
of on-chip ROM (if on-chip ROM is enabled) and the value
programmed into the ROMBR register. It is active when an
external master has control of the bus, as well as when the
Z80185 processor is in control.
XTAL. Crystal (input, active High). This pin functions as the
Crystal oscillator connection and should be left open if an
external clock is used instead of a crystal. The oscillator
input is not a TTL level (reference DC Characteristics
section).
EXTAL. External Clock/Crystal (input, active High). This
pin functions as a Crystal oscillator connection. An exter-
nal clock can be input to the Z80185 on this pin when a
crystal is not used. This input is Schmitt-triggered.
PHI. System Clock (output, active High). This output is the
processor’s reference clock, and is provided for the use of
external logic. The frequency of this output may be equal
to, or one-half that of the crystal or input clock frequency,
depending on an internal register bit.
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