Z80185 Datasheet, PDF (77/95 Pages) Zilog, Inc. – SMART PERIPHERAL CONTROLLERS

Zilog
PRELIMINARY
Z80185/Z80195
SMART PERIPHERAL CONTROLLES
Z80185 BIDIRECTIONAL CENTRONICS P1284 CONTROLLER (Continued)
Host ECP Reverse Modes
1. In these modes the controller configures PIA27-20 as
inputs, regardless of the contents of register E2. On
entry to one of these modes, the controller clears the
Idle bit, if it had been set.
2. For each byte, the controller waits for the peripheral to
drive PeriphClk (nAck) Low. When this happens, and
software, or the DMA channel, has taken any previous
byte from the Input/Output Register and thus cleared
DREQ, operation diverges into four cases, depending
on the state of PeriphAck (Busy), the mode, the LS bit
of the data, and the state of an internal 7-bit RLE
counter.
If PeriphAck (Busy) is High, indicating that this byte is
neither an RLE value nor a Channel Address, the
controller captures the data from PIA27-20 in the IOR,
sets DREQ to notify software, or the DMA channel to
take the byte, and drives HostAck (nAutoFd) High. If the
RLE counter is zero, the controller then waits (if neces-
sary) for the peripheral to drive PeriphClk (nAck) back
to High, after which it drives HostAck (nAutoFd) back to
Low and returns to the event sequence at the start of
paragraph #2. If the RLE counter is non-zero, the
controller waits for software, or the DMA channel, to
read the byte from the IOR, negates DREQ only mo-
mentarily, and decrements the RLE counter. It does this
until the RLE counter is zero, at which point it proceeds
as described above. Thus an RLE value of “n” results in
the next byte being provided to software or a DMA
channel “n+1” times.
3. If PeriphAck (Busy) is Low, and the MSbit of the byte is
zero (PIA27 is Low), the byte is an RLE repeat count. If
the mode is “hardware RLE expansion,” the controller
transfers (the seven LSbits of) it to the RLE counter,
leaves DREQ cleared, and drives HostAck (nAutoFd)
High. Thereafter the controller waits for the peripheral to
drive PeriphClk (nAck) back to High, at which time it
drives HostAck (nAutoFd) back to Low and returns to
the event sequence at the start of paragraph #2.
4. If PeriphAck (Busy) is Low, and the MSbit of the byte is
1 (PIA27 is High), the byte is a “channel address”. In this
case, or when the LSbit is zero, but the mode is
“software RLE handling," the controller captures the
data from PIA27-20 in the IOR, leaves DREQ cleared, to
keep a DMA channel from storing the byte, and sets
Idle, which it does not otherwise set in this mode.
Software should respond to this condition by reading
the byte from the PIA 2 data register E3, reprogramming
a DMA channel, if necessary, and doing whatever else
is needed to handle the channel address, and finally
setting HostAck (nAutoFd) High. Thereafter the control-
ler clears Idle, waits for the peripheral to drive PeriphClk
(nAck) back to High, and then drives HostAck (nAutoFd)
back to Low, and returns to the start of the event
sequence in paragraph #2 above.
5. If data has become available to be sent while this mode
is in effect and software elects to send it, it should drive
nReverseRequest (nInit) to High, set Host Negotiation
mode to take full control of the interface, wait for
nAckReverse (PError) to go High, and then set PIA27-
20 as outputs.
6. Status interrupts in Host ECP Reverse mode include
rising and falling edges on nPeriphRequest (nFault).
nPeriphRequest carries a valid “reverse data available”
indication during Reverse ECP mode. If so, enable
status interrupts during this mode; if not, disable them.
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