DS90UB964-Q1 Datasheet, PDF (91/116 Pages) Texas Instruments – DS90UB964-Q1 Quad FPD-Link III Deserializer Hub

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DS90UB964-Q1
SNLS500 – JULY 2016
8.7.1 Indirect Access Registers
Several functional blocks include register sets contained in the Indirect Access map (Table 13); i.e. Pattern
Generator, CSI-2 timing, and Analog controls. Register access is provided via an indirect access mechanism
through the Indirect Access registers (IND_ACC_CTL, IND_ACC_ADDR, and IND_ACC_DATA). These registers
are located at offsets 0xB0-0xB2 in the main register space.
The indirect address mechanism involves setting the control register to select the desired block, setting the
register offset address, and reading or writing the data register. In addition, an auto-increment function is
provided in the control register to automatically increment the offset address following each read or write of the
data register.
For writes, the process is as follows:
1. Write to the IND_ACC_CTL register to select the desired register block
2. Write to the IND_ACC_ADDR register to set the register offset
3. Write the data value to the IND_ACC_DATA register
If auto-increment is set in the IND_ACC_CTL register, repeating step 3 will write additional data bytes to
subsequent register offset locations
For reads, the process is as follows:
1. Write to the IND_ACC_CTL register to select the desired register block
2. Write to the IND_ACC_ADDR register to set the register offset
3. Read from the IND_ACC_DATA register
If auto-increment is set in the IND_ACC_CTL register, repeating step 3 will read additional data bytes from
subsequent register offset locations.
IA Select
0xB0[5:2]
0000
0001
0010
0011
0100
0101
0110
0111
Page/Block
0
1
2
3
4
5
6
7
Table 13. Indirect Register Map Description
Indirect Registers
Digital Page 0 Indirect Registers
FPD3 Channel 0 Reserved Registers
FPD3 Channel 1 Reserved Registers
FPD3 Channel 2 Reserved Registers
FPD3 Channel 3 Reserved Registers
FPD3 Share Reserved Registers
Write All FPD3 Reserved Registers
CSI TX Reserved Registers
Address Range
Description
0x01-0x1F
0x40-0x51
0x60-0x71
0x00-0x14
0x00-0x14
0x00-0x14
0x00-0x14
0x00-0x04
0x00-0x14
0x00-0x1D
Pattern Gen Registers
CSI TX port 0 Timing Registers
CSI TX port 1 Timing Registers
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
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