DS90UB964-Q1 Datasheet, PDF (85/116 Pages) Texas Instruments – DS90UB964-Q1 Quad FPD-Link III Deserializer Hub

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DS90UB964-Q1
SNLS500 – JULY 2016
Register Maps (continued)
Table 12. Serial Control Bus Registers (continued)
Page Addr Register Name
(hex)
Bit(s) Field
3
MODE_DONE
Type
R
2:0 MODE
R
Share 0xB9 LINK_ERROR_COU 7:6 RESERVED
R
NT
5
LINK_SFIL_WAIT
RW
4
LINK_ERR_COUNT_ RW
EN
3:0 LINK_ERR_THRESH RW
Share 0xBC FV_MIN_TIME
7:0 FRAME_VALID_MIN RW
Share 0xBE GPIO_PD_CTL
7
GPIO7_PD_DIS
RW
6
GPIO6_PD_DIS
RW
5
GPIO5_PD_DIS
RW
Default Description
1
Strap
0x0
MODE Done
If set, indicates the MODE decode has
completed and latched into the MODE status
bits.
MODE Decode
3-bit decode from MODE pin
Reserved
0
0
0x3
0x80
0
0
0
During SFILTER adaption, setting this bit will
cause the Lock detect circuit to ignore errors
during the SFILTER wait period after the
SFILTER control is updated.
1: Errors during SFILTER Wait period will be
ignored
0: Errors during SFILTER Wait period will not
be ignored and may cause loss of Lock
Enable serial link data integrity error count
1: Enable error count
0: DISABLE
Link error count threshold.
The Link Error Counter monitors the forward
channel link and determines when link will be
dropped. The link error counter is pixel clock
based. clk0, clk1, parity, and DCA are
monitored for link errors. If the error counter is
enabled, the deserializer will lose lock once the
error counter reaches the
LINK_ERR_THRESH value. If the link error
counter is disabled, the deserilizer will lose
lock after one error. The control bits in
DIGITAL_DEBUG_2 register can be used to
disable error conditions individually.
Frame Valid Minimum Time
This register controls the minimum time the
FrameValid (FV) should be active before the
Raw mode FPD3 receiver generates a
FrameStart packet. Duration is in FPD3 clock
periods.
GPIO7 Pull-down Resistor Disable:
The GPIO pins by default include a pulldown
resistor that is automatically enabled when the
GPIO is not in an output mode. When this bit is
set, the pulldown resistor will also be disabled
when the GPIO pin is in an input only mode.
1 : Disable GPIO pull-down resistor
0 : Enable GPIO pull-down resistor
GPIO6 Pull-down Resistor Disable:
The GPIO pins by default include a pulldown
resistor that is automatically enabled when the
GPIO is not in an output mode. When this bit is
set, the pulldown resistor will also be disabled
when the GPIO pin is in an input only mode.
1 : Disable GPIO pull-down resistor
0 : Enable GPIO pull-down resistor
GPIO5 Pull-down Resistor Disable:
The GPIO pins by default include a pulldown
resistor that is automatically enabled when the
GPIO is not in an output mode. When this bit is
set, the pulldown resistor will also be disabled
when the GPIO pin is in an input only mode.
1 : Disable GPIO pull-down resistor
0 : Enable GPIO pull-down resistor
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