DS90UB964-Q1 Datasheet, PDF (10/116 Pages) Texas Instruments – DS90UB964-Q1 Quad FPD-Link III Deserializer Hub

DS90UB964-Q1
SNLS500 – JULY 2016
6.7 AC Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
PARAMETER
TEST CONDITIONS
PIN OR
FREQUENCY
MIN
LVCMOS I/O
t_CLH
LVCMOS Low-to-High
Transition Time
t_CHL
LVCMOS High-to-Low
Transition Time
VDDIO: 1.71 V to 1.89 V
OR
VDDIO: 3.0 V to 3.6 V
C_L = 8 pF (lumped load)
Default Registers
(Figure 1)
GPIO[7:0]
GPIO[7:0]
FPD-LINK III RECEIVER INPUT
t_DDLT
IJT
Deserializer Data Lock Time
Input Jitter Tolerance⁽¹⁾
With Adaptive Equalization
(Figure 3)
Jitter Frequency >
FPD3_PCLK⁽²⁾ / 15
See Input Jitter Tolerance
RIN0±, RIN1±,
RIN2±, RIN3±
(1) Specification is ensured by design and/or characterization and is not tested in production.
(2) FPD3_PCLK is equivalent to PCLK frequency based on the operating MODE:
10-bit mode: PCLK_Freq. /2
12-bit HF mode: PCLK_Freq. x 2/3
12-bit LF mode: PCLK_Freq.
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TYP
MAX UNIT
2.5
ns
2.5
ns
15
22 ms
0.4 UI
10
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