DS90UB964-Q1 Datasheet, PDF (70/116 Pages) Texas Instruments – DS90UB964-Q1 Quad FPD-Link III Deserializer Hub

DS90UB964-Q1
SNLS500 – JULY 2016
www.ti.com
Register Maps (continued)
Page Addr Register Name
(hex)
CSI 0x34 CSI_CTL2
CSI 0x35 CSI_STS
Table 12. Serial Control Bus Registers (continued)
Bit(s) Field
Type Default Description
3:2 CSI_ULP
RW
0
Force LP00 state on data/clock lanes
00: Normal operation
01: LP00 state forced only on data lanes
10: Reserved
11: LP00 state forced on data and clock lanes
1
CSI_CONTS_CLOCK RW
0
Enable CSI continuous clock mode
0: Disabled
1: Enabled
0
CSI ENABLE
RW
0
Enable CSI output
0: Disabled
1: Enabled
7:4 RESERVED
R
0x0
Reserved
3
CSI_PASS_MODE RW
0
CSI PASS indication mode
Determines whether the CSI Pass indication is
for a single port or all enabled ports.
0 : Assert PASS if at least one enabled
Receive port is providing valid video data
1 : Assert PASS only if ALL enabled Receive
ports are providing valid video data
2
CSI_CAL_INV
RW
0
CSI Calibration Inverted Data pattern
During the CSI skew-calibration pattern, the
CSI Transmitter will send a sequence of
01010101 data (first bit 0). Setting this bit to a
1 will invert the sequence to 10101010 data.
1
CSI_CAL_SINGLE RW
0
Enable single periodic CSI Skew-Calibration
sequence
Setting this bit will send a single skew-
calibration sequence from the CSI Transmitter.
The skew-calibration sequence is the 1010 bit
sequence required for periodic calibration. The
calibration sequence is sent at the next idle
period on the CSI interface. This bit is self-
clearing and will reset to 0 after the calibration
sequence is sent.
0
CSI_CAL_PERIODIC RW
0
Enable periodic CSI Skew-Calibration
sequence
When the periodic skew-calibration sequence
is enabled, the CSI Transmitter will send the
periodic skew-calibration sequence following
the sending of Frame End packets.
0: Disabled
1: Enabled
7:5 RESERVED
R
0x0
Reserved
4
TX_PORT_NUM
R
0
TX Port Number
This read-only field indicates the number of the
currently selected TX read port.
3:2 RESERVED
R
0x0
Reserved
1
TX_PORT_SYNC
R
0
TX Port Synchronized
This bit indicates the CSI Transmit Port is able
to properly synchronize input data streams
from multiple sources. This bit is 0 if
synchronization is disabled via the FWD_CTL2
register.
0 : Input streams are not synchronized
1 : Input streams are synchronized
70
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