DS90UB964-Q1 Datasheet, PDF (84/116 Pages) Texas Instruments – DS90UB964-Q1 Quad FPD-Link III Deserializer Hub

DS90UB964-Q1
SNLS500 – JULY 2016
www.ti.com
Register Maps (continued)
Table 12. Serial Control Bus Registers (continued)
Page Addr Register Name
(hex)
Share 0xB1 IND_ACC_ADDR
Share 0xB2 IND_ACC_DATA
Share 0xB3 BIST Control
Share 0xB8 MODE_IDX_STS
Bit(s) Field
Type Default Description
5:2 IA_SEL
RW
1
IA_AUTO_INC
RW
0
IA_READ
RW
7:0 IA_ADDR
RW
7:0 IA_DATA
RW
7:6 BIST_OUT_MODE RW
5:4 RESERVED
RW
3
BIST PIN CONFIG RW
2:1 BIST CLOCK
RW
SOURCE
0
BIST_EN
RW
7
IDX_DONE
R
6:4 IDX
R
0x0
0
0
0x0
0x0
0x0
0x0
1
0
0
1
Strap
Indirect Access Register Select:
Selects target for register access
0000 : CSI-2 Pattern Generator & Timing
Registers
(See Table 14)
0001 : FPD3 RX Port 0 Reserved Registers
0010 : FPD3 RX Port 1 Reserved Registers
0011 : FPD3 RX Port 2 Reserved Registers
0100 : FPD3 RX Port 3 Reserved Registers
0101 : FPD3 RX Shared Reserved Registers
0110 : Simultaneous write to FPD3 RX
Reserved Registers
0111 : CSI-2 Reserved Registers
Indirect Access Auto Increment:
Enables auto-increment mode. Upon
completion of a read or write, the register
address will automatically be incremented by 1
Indirect Access Read:
Setting this allows generation of a read strobe
to the selected register block upon setting of
the IND_ACC_ADDR register. In auto-
increment mode, read strobes will also be
asserted following a read of the
IND_ACC_DATA register. This function is only
required for blocks that need to pre-fetch
register data.
Indirect Access Register Offset:
This register contains the 8-bit register offset
for the indirect access.
Indirect Access Data:
Writing this register will cause an indirect write
of the IND_ACC_DATA value to the selected
analog block register. Reading this register will
return the value of the selected block register
BIST Output Mode
00 : No toggling
01 : Alternating 1/0 toggling
1x : Toggle based on BIST data
Reserved
Bist Configured through Pin.
1: Bist configured through pin.
0: Bist configured through bits 2:0 in this
register
BIST Clock Source
This register field selects the BIST Clock
Source at the Serializer. These register bits are
automatically written to the CLOCK SOURCE
bits (register offset 0x14) in the Serializer after
BIST is enabled. See the appropriate Serializer
register descriptions for details.
BIST Control
1: Enabled
0: Disabled
IDX Done
If set, indicates the IDX decode has completed
and latched into the IDX status bits.
IDX Decode
3-bit decode from IDX pin
84
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