DS90UB964-Q1 Datasheet, PDF (32/116 Pages) Texas Instruments – DS90UB964-Q1 Quad FPD-Link III Deserializer Hub

DS90UB964-Q1
SNLS500 – JULY 2016
GPIOx
Serializer
FPD-Link III
HUB Deserializer
BC_GPIOx
GPIOx
Serializer
FPD-Link III
BC_GPIOx
GPIOx
Serializer
FPD-Link III
BC_GPIOx
GPIOx
Serializer
FPD-Link III
BC_GPIOx
FrameSync
Generator
Figure 28. Internal FrameSync
FS_HIGH
FS_LOW
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FS_LOW = FS_LOW_TIME * FS_CLK_PD
FS_HIGH = FS_HIGH_TIME * FS_CLK_PD
where FS_CLK_PD is the resolution of the FrameSync generator clock
Figure 29. Internal FrameSync Signal
The following example shows generation of a FrameSync signal at 60 pulses per second. Mode settings:
• Programmable High/Low periods: FS_GEN_MODE 0x18[1]=0
• Use port 0 back channel frame period: FS_MODE 0x18[7:4]=0x0
• Back channel rate of 2.5 Mbps: BC_FREQ_SELECT for port 0 0x58[2:0]=0x0
• Initial FS state of 0: FS_INIT_STATE 0x18[2]=0
Based on mode settings, the FrameSync is generated based upon FS_CLK_PD of 12 us.
The total period of the FrameSync is (1 sec / 60 hz) / 12 µs or approximately 1,389 counts.
For a 10% duty cycle, set the high time to 139 (0x008A) cycles, and the low time to 1,250 (0x04E1) cycles:
• FS_HIGH_TIME_1: 0x19=0x00
• FS_HIGH_TIME_0: 0x1A=0x8A
• FS_LOW_TIME_1: 0x1B=0x04
• FS_LOW_TIME_0: 0x1C=0xE1
8.4.18.2.1 Code Example for Internally Generated FrameSync
WriteI2C(0x4C,0x01) # RX0
WriteI2C(0x6E,0xAA) # BC_GPIO_CTL0: FrameSync signal to GPIO0/1
WriteI2C(0x4C,0x12) # RX1
WriteI2C(0x6E,0xAA) # BC_GPIO_CTL0: FrameSync signal to GPIO0/1
WriteI2C(0x4C,0x24) # RX2
WriteI2C(0x6E,0xAA) # BC_GPIO_CTL0: FrameSync signal to GPIO0/1
WriteI2C(0x4C,0x38) # RX3
WriteI2C(0x6E,0xAA) # BC_GPIO_CTL0: FrameSync signal to GPIO0/1
WriteI2C(0x10,0x91) # FrameSync signal; Device Status; Enabled
WriteI2C(0x58,0x58) # BC FREQ SELECT: 2.5 Mbps
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