DS90UB964-Q1 Datasheet, PDF (75/116 Pages) Texas Instruments – DS90UB964-Q1 Quad FPD-Link III Deserializer Hub

www.ti.com
DS90UB964-Q1
SNLS500 – JULY 2016
Register Maps (continued)
Table 12. Serial Control Bus Registers (continued)
Page Addr Register Name
(hex)
RX 0x4F RX_FREQ_HIGH
RX 0x50 RX_FREQ_LOW
RX 0x55 RX_PAR_ERR_HI
RX 0x56 RX_PAR_ERR_LO
RX 0x57 BIST_ERR_COUNT
RX 0x58 BCC_CONFIG
Bit(s) Field
Type Default Description
2
FREQ_STABLE
R
0
1
NO_FPD3_CLK
R
0
0
LINE_CNT_CHG
R/COR 0
7:0 FREQ_CNT_HIGH R
0x0
7:0 FREQ_CNT_LOW R
0x0
7:0 PAR ERROR BYTE 1 R
0x0
7:0 PAR ERROR BYTE 0 R
0x0
7:0 BIST ERROR
COUNT
7
I2C PASS
THROUGH ALL
6
I2C PASS
THROUGH
5
AUTO ACK ALL
R
0x0
RW
0
RW
0
RW
0
4
BC_ALWAYS_ON RW
1
Frequency measurement stable
No FPD-Link III input clock detected
Line Count Changed
1: Change of line count detected
0: Change of line count not detected
This bit is cleared on read.
Frequency Counter High Byte (MHz)
The Frequency counter reports the measured
frequency for the FPD3 Receiver. This portion
of the field is the integer value in MHz.
Frequency Counter Low Byte (1/256 MHz)
The Frequency counter reports the measured
frequency for the FPD3 Receiver. This portion
of the field is the fractional value in 1/256 MHz.
Number of FPD3 parity errors – 8 most
significant bits
The parity error counter registers return the
number of data parity errors that have been
detected on the FPD3 Receiver data since the
last detection of valid lock or last read of the
RX_PAR_ERR_LO register. For accurate
reading of the parity error count, disable the
RX PARITY CHECKER ENABLE bit in register
0x2 prior to reading the parity error count
registers. This register is cleared upon reading
the RX_PAR_ERR_LO register.
Number of FPD3 parity errors – 8 least
significant bits
The parity error counter registers return the
number of data parity errors that have been
detected on the FPD3 Receiver data since the
last detection of valid lock or last read of the
RX_PAR_ERR_LO register. For accurate
reading of the parity error count, disable the
RX PARITY CHECKER ENABLE bit in register
0x2 prior to reading the parity error count
registers. This register is cleared on read.
Bist Error Count
Returns BIST error count
I2C Pass-Through All Transactions
0: Disabled
1: Enabled
I2C Pass-Through to Serializer if decode
matches
0: Pass-Through Disabled
1: Pass-Through Enabled
Automatically Acknowledge all I2C writes
independent of the forward channel lock state
or status of the remote Acknowledge
1: Enable
0: Disable
Back channel enable
1: Back channel is always enabled
independent of I2C_PASS_THROUGH and
I2C_PASS_THROUGH_ALL
0: Back channel enable requires setting of
either I2C_PASS_THROUGH and
I2C_PASS_THROUGH_ALL This bit may only
be written via a local I2C master.
Copyright © 2016, Texas Instruments Incorporated
Product Folder Links: DS90UB964-Q1
Submit Documentation Feedback
75