DS90UB964-Q1 Datasheet, PDF (13/116 Pages) Texas Instruments – DS90UB964-Q1 Quad FPD-Link III Deserializer Hub

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DS90UB964-Q1
SNLS500 – JULY 2016
AC Electrical Characteristics (continued)
Over recommended operating supply and temperature ranges unless otherwise specified.
PARAMETER
TEST CONDITIONS
PIN OR
FREQUENCY
MIN
LPTX DRIVER
t_RLP
t_FLP
t_REOT
Rise Time LP⁽¹⁾⁽²⁾
Fall Time LP ⁽¹⁾⁽²⁾
Rise Time Post-EoT^{(1) (2)}
15% to 85% rise time
15% to 85% fall time
30%-85% rise time
First LP exclusive-OR clock pulse
t_LP-PULSE-TX
Pulse width of the LP exclusive- ^{after Stop state or last pulse}
OR clock^{(1) (2)}
before Stop state
40
All other pulses
20
t_LP-PER-TX
DV/DtSR
Period of the LP exclusive-OR
clock ⁽¹⁾
Slew rate ⁽¹⁾⁽²⁾
C_LOAD = 0 pF
C_LOAD = 5 pF
C_LOAD = 20 pF
C_LOAD = 70 pF
C_LOAD = 0 to 70 pF (Falling Edge
Only)
C_LOAD = 0 to 70 pF (Rising Edge
Only)
CSI0_D0P/N
CSI0_D1P/N
CSI0_D2P/N
CSI0_D3P/N
CSI1_D0P/N
CSI1_D1P/N
CSI1_D2P/N
CSI1_D3P/N
CSI0_CLKP/N
CSI1_CLKP/N
C_LOAD = 0 to 70 pF (Rising Edge
Only) ^{(3) (4)}
90
30
30
30 -
0.075×(
VO,INS
T - 700)
C_LOAD = 0 to 70 pF (Rising Edge
Only) ^{(5) (6)}
C_LOAD
Load capacitance⁽¹⁾⁽²⁾
CSI-2 TIMING SPECIFICATIONS — DATA-CLOCK TIMING (Figure 6, Figure 7)
UI_INST
UI instantaneous⁽¹⁾
In 1, 2, 3, or 4 Lane
Configuration
HS Data rate = 400 Mbps
25 -
0.0625×
(VO,IN
ST -
500)
0
ΔUI
t_SKEW(TX)
UI variation⁽¹⁾
Data to Clock Skew (measured
at transmitter)⁽¹⁾
Skew between clock and data
from ideal center
In 1, 2, 3, or 4 Lane
Configuration
HS Data rate = 800 Mbps
CSI0_D0P/N
In 1, 2, 3, or 4 Lane
Configuration
CSI0_D1P/N
CSI0_D2P/N
HS Data rate = 1.6 Gbps
CSI0_D3P/N
UI ≥ 1 ns (Figure 5)
CSI1_D0P/N
UI < 1 ns (Figure 5)
CSI1_D1P/N
CSI1_D2P/N
HS Data rate ≤ 1 Gbps (Figure 5) _{CSI1_D3P/N}
1 Gbps ≤ HS Data rate ≤ 1.5
Gbps (Figure 5)
CSI0_CLKP/N
CSI1_CLKP/N
-10%
-5%
-0.15
-0.2
t_SKEW(TX)
static
Static Data to Clock Skew⁽¹⁾
HS Data rate > 1.5 Gbps
-0.2
t_SKEW(TX)
dynamic
Dynamic Data to Clock Skew⁽¹⁾ HS Data rate > 1.5 Gbps
-0.15
TYP
2.5
1.25
0.625
MAX UNIT
25 ns
25 ns
35 ns
ns
ns
ns
500 mV/ns
300 mV/ns
250 mV/ns
150 mV/ns
mV/ns
mV/ns
mV/ns
mV/ns
70 pF
ns
ns
ns
10%
5%
0.15
UI
UI
UI_INST
0.2 UI_INST
0.2 UI_INST
0.15 UI_INST
(2) C_LOAD includes the low-frequency equivalent transmission line capacitance. The capacitance of TX and RX are assumed to always be
<10 pF. The distributed line capacitance can be up to 50 pF for a transmission line with 2ns delay.
(3) When the output voltage is between 700 mV and 930 mV
(4) Applicable when the supported data rate ≤ 1.5 Gbps
(5) When the output voltage is between 550 mV and 790 mV
(6) Applicable when the supported data rate > 1.5 Gbps.
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